公开(公告)号：US06337821B1

公开(公告)日：2002-01-08

申请号：US09636504

申请日：2000-08-10

申请人： Yohji Watanabe ,  Kenji Tsuchida

发明人： Yohji Watanabe ,  Kenji Tsuchida

IPC分类号： G11C706

CPC分类号： G11C7/106 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096

摘要： A data input/output buffer is connected between first data lines and second data lines. An equalizing circuit and a data latch circuit are connected to the second data lines. The equalizing circuit maintains the second data lines in reset condition, during normal operation. It temporarily releases the second data lines from the reset condition, in response to an output from an address-transition detecting circuit, thereby to transfer the data from the data input/output buffer. The data latch circuit latches the data transferred to the second data lines, in response to the output from the address-transition detecting circuit.

摘要翻译： 数据输入/输出缓冲器连接在第一数据线和第二数据线之间。 均衡电路和数据锁存电路连接到第二数据线。 均衡电路在正常工作期间将第二条​​数据线保持在复位状态。 它响应于地址转换检测电路的输出暂时从复位状态释放第二数据线，从而从数据输入/输出缓冲器传送数据。 数据锁存电路根据地址转换检测电路的输出锁存传送到第二数据线的数据。

公开(公告)号：US6108254A

公开(公告)日：2000-08-22

申请号：US150782

申请日：1993-11-12

申请人： Yohji Watanabe ,  Kenji Tsuchida

发明人： Yohji Watanabe ,  Kenji Tsuchida

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C7/10 ,  G11C11/407

CPC分类号： G11C7/106 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/22

摘要： A Dynamic Random Access Memory (DRAM) in which a data input/output buffer is connected between first data lines and second data lines. An equalizing circuit and a data latch circuit are connected to the second data lines. The equalizing circuit maintains the second data lines in reset condition, during normal operation. It temporarily releases the second data lines from the reset condition, in response to an output from an address-transition detecting circuit, thereby to transfer the data from the data input/output buffer. The data latch circuit latches the data transferred to the second data lines, in response to the output from the address-transition detecting circuit.

摘要翻译： 动态随机存取存储器（DRAM），其中数据输入/输出缓冲器连接在第一数据线和第二数据线之间。 均衡电路和数据锁存电路连接到第二数据线。 均衡电路在正常工作期间将第二条​​数据线保持在复位状态。 它响应于地址转换检测电路的输出暂时从复位状态释放第二数据线，从而从数据输入/输出缓冲器传送数据。 数据锁存电路根据地址转换检测电路的输出锁存传送到第二数据线的数据。

公开(公告)号：US5289413A

公开(公告)日：1994-02-22

申请号：US712106

申请日：1991-06-07

申请人： Kenji Tsuchida ,  Yohji Watanabe

发明人： Kenji Tsuchida ,  Yohji Watanabe

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G11C7/1033 ,  G11C7/1006

摘要： A MOS memory device includes an array of rows and columns of memory cells, word lines connected to the rows of memory cells, and a plurality of pairs of bits lines connected to the columns. Sense amplifiers and transfer gates are provided for every bit line pair. A column decoder has outputs connected via column-select lines to transfer gates such that each output is connected to two adjacent gates. When activating a certain column, the column decoder potentially activates another column adjacent to the certain column before actually receiving the corresponding column address. This permits information bits stored in four memory cells to be transferred simultaneously to the registers and latched therein. A multiplexer serially reads out the latched information bits. The column preactivation improves the serial accessing speed of the memory device.

摘要翻译： MOS存储器件包括存储器单元的行和列的阵列，连接到存储器单元的行的字线以及连接到列的多对位线。 为每个位线对提供感测放大器和传输门。 列解码器具有通过列选择线连接的输出以传送门，使得每个输出连接到两个相邻的门。 当激活某个列时，列解码器在实际接收相应的列地址之前潜在地激活与特定列相邻的另一列。 这允许存储在四个存储单元中的信息位同时传送到寄存器并锁存在其中。 多路复用器串行读出锁存的信息位。 列预激活提高了存储设备的串行访问速度。

公开(公告)号：US20080079473A1

公开(公告)日：2008-04-03

申请号：US11864041

申请日：2007-09-28

申请人： Fumiyoshi Matsuoka ,  Yohji Watanabe ,  Ryo Fukuda

发明人： Fumiyoshi Matsuoka ,  Yohji Watanabe ,  Ryo Fukuda

IPC分类号： H03K3/356

CPC分类号： H03K3/356191 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104

摘要： A second-conductivity-type transistor includes a source and drain formed by a second-conductivity-type diffusion layer formed on a first-conductivity-type semiconductor layer; and a gate formed on the first-conductivity-type semiconductor layer sandwiched between the second-conductivity-type diffusion layer through an insulating film A first-conductivity-type transistor includes a source and drain formed by a first-conductivity-type diffusion layer formed on a second-conductivity-type semiconductor layer; and a gate formed on the second-conductivity-type semiconductor layer sandwiched between the first-conductivity-type diffusion layer through an insulating film. The second-conductivity-type diffusion layer for configuring the second-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the first-conductivity-type semiconductor layer. The first-conductivity-type diffusion layer for configuring the first-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the second-conductivity-type semiconductor layer.

摘要翻译： 第二导电型晶体管包括由形成在第一导电型半导体层上的第二导电型扩散层形成的源极和漏极; 并且通过绝缘膜夹在第二导电型扩散层之间的第一导电型半导体层上形成的栅极第一导电型晶体管包括由形成的第一导电型扩散层形成的源极和漏极 在第二导电型半导体层上; 以及形成在通过绝缘膜夹在第一导电型扩散层之间的第二导电型半导体层上的栅极。 用于构造第二导电型晶体管的第二导电型扩散层被分成多个区域，每个区域被形成在第一导电型半导体层上的器件隔离区分隔开。 用于构造第一导电型晶体管的第一导电型扩散层被分成多个区域，每个区域被形成在第二导电类型半导体层上的器件隔离区隔开。

公开(公告)号：US06603689B2

公开(公告)日：2003-08-05

申请号：US10045780

申请日：2002-01-11

申请人： Daisuke Kato ,  Yohji Watanabe

发明人： Daisuke Kato ,  Yohji Watanabe

IPC分类号： G11C700

CPC分类号： G11C29/787

摘要： A semiconductor memory device having a memory system and a redundancy system including redundant elements for repairing a plurality of defects in the memory system, comprising a plurality of address fuse sets each including address fuses for programming a defective address in the memory system, and a master fuse for preventing a corresponding redundant element from being selected when the redundant element is not used, wherein at least one master fuse is shared by at least two fuse sets among the plurality of address fuse sets.

公开(公告)号：US5546349A

公开(公告)日：1996-08-13

申请号：US403265

申请日：1995-03-13

申请人： Yohji Watanabe ,  John K. DeBrosse

发明人： Yohji Watanabe ,  John K. DeBrosse

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C7/18 ,  G11C11/409 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C7/10 ,  G11C7/18

摘要： An exchangeable hierarchical data line structure includes a first half of a unit circuit, a second half of a unit circuit and a common sense amplifier row disposed therebetween. The common sense amplifier row includes a common plurality of sense amplifiers and a common local data line. The structure includes a first set of master data lines with a first master data line and a third master data line, and a second set of master data lines with a second master data line and a fourth master data line. The master data lines form a master bus transversing the direction of the common local data line. The structure includes first switch circuitry to selectively couple signals between the common local data line and the first master data line. The structure includes second switch circuitry to selectively couple signals between the common local data line and the second master data line. A signal on the common local data line is couplable to the first master data line when the signal on the common local data line is not coupled to the second master data line, and the signal on the common data line is couplable to the second master data line when the signal on the common local data line is not coupled to first master data line.

摘要翻译： 可交换的分层数据线结构包括单元电路的前半部分，单元电路的后半部分和设置在它们之间的公共读出放大器行。 常读放大器行包括公共多个读出放大器和公共本地数据线。 该结构包括具有第一主数据线和第三主数据线的第一组主数据线，以及具有第二主数据线和第四主数据线的第二组主数据线。 主数据线形成主总线，横切公共本地数据线的方向。 该结构包括用于选择性地在公共本地数据线和第一主数据线之间耦合信号的第一开关电路。 该结构包括用于选择性地在公共本地数据线和第二主数据线之间耦合信号的第二开关电路。 当公共本地数据线上的信号未耦合到第二主数据线时，公共本地数据线上的信号可耦合到第一主数据线，并且公共数据线上的信号可耦合到第二主数据 当公共本地数据线上的信号未耦合到第一主数据线时。

公开(公告)号：US5544113A

公开(公告)日：1996-08-06

申请号：US346965

申请日：1994-11-30

申请人： Toshiaki Kirihata ,  Yohji Watanabe

发明人： Toshiaki Kirihata ,  Yohji Watanabe

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/808

摘要： A wide Input/Output (I/O) Random Access Memory (RAM) with more efficient redundancy. The RAM array may be divided into individual units. Each unit is further divided into subarray blocks (blocks of subarrays). Each subarray or segment is organized by one and includes one spare column and may include spare word lines. When a block is accessed, only half of the segments are accessed. Whenever a segment is accessed, the segment's spare column is not. The spare columns from the unaccessed half block are available for repairing defective columns in the accessed half block. Data from columns in the accessed half and spare columns in the unaccessed half are transferred to Local Data Lines (LDLs) and from LDLs to Master Data Lines (MDLs). Valid data from accessed column lines and from selected spare lines are provided on the MDLS to second sense amplifiers. Defective columns are electrically replaced with spares after the second stage amplifiers. Thus, all of the spare columns in each half of each subarray block are available to replace an equal number of failed columns at any location in any segment in the other half block.

摘要翻译： 具有更高效冗余的宽输入/输出（I / O）随机存取存储器（RAM）。 RAM阵列可以被分成单独的单元。 每个单元进一步分为子阵列（子阵列）。 每个子阵列或段由一个组成，并且包括一个备用列，并且可以包括备用字线。 访问块时，仅访问一半的段。 无论何时访问段，段的备用列都不存在。 来自未加工的半块的备用列可用于修复访问的半块中的有缺陷的列。 未访问的一半中的列中的数据和未加工的一半中的备用列的数据将传输到本地数据线（LDL），并从LDL传输到主数据线（MDL）。 在MDLS上向第二读出放大器提供来自所访问列线和选定备用线路的有效数据。 在第二级放大器之后，有缺陷的列被替换为备件。 因此，每个子阵列块的每一半中的所有备用列可用于在另一半块中的任何段中的任何位置处替换相等数量的故障列。

公开(公告)号：US4814686A

公开(公告)日：1989-03-21

申请号：US12345

申请日：1987-02-09

申请人： Yohji Watanabe

发明人： Yohji Watanabe

IPC分类号： H01L27/04 ,  G05F3/24 ,  H01L21/822

CPC分类号： G05F3/247

摘要： A reference d.c. voltage generator is disclosed which includes a series circuit for first and second field effect transistors or FETs. The first FET serves as a high-impedance constant current supply, while the second FET functions as a resistor for generating at its soure a reference d.c. voltage. A series circuit of two FETs is connected between the gate and source of the first FET to bias the first FET such that a current flowing therein is kept constant, whereby the gate-source voltage thereof can be stabilized even when the power supply voltage is fluctuated.

摘要翻译： 参考文献 公开了一种电压发生器，其包括用于第一和第二场效应晶体管或FET的串联电路。 第一个FET用作高阻抗恒流源，而第二个FET用作电阻器，用于产生一个参考直流电流。 电压。 两个FET的串联电路连接在第一FET的栅极和源极之间以偏置第一FET，使得流过其中的电流保持恒定，由此即使当电源电压波动时，其栅极 - 源极电压也能够稳定 。

公开(公告)号：US08027216B2

公开(公告)日：2011-09-27

申请号：US12550663

申请日：2009-08-31

申请人： Ryo Fukuda ,  Yohji Watanabe

发明人： Ryo Fukuda ,  Yohji Watanabe

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C8/04 ,  G11C11/406 ,  G11C11/40615 ,  G11C2211/4016 ,  G11C2211/4067

摘要： A memory may includes: word lines; bit lines; memory array blocks including memory cells, each memory array block being a unit of a data read operation or a data write operation; a row decoder configured to selectively drive the word lines; sense amplifiers configured to detect data; and an access counter provided for each memory cell block, the access counter counting the number of times of accessing the memory array blocks in order to read data or write data, and activating a refresh request signal when the number of times of access reaches a predetermined number of times, wherein during an activation period of the refresh request signal of the access counter, the row decoder periodically and sequentially activates the word lines of the memory array blocks corresponding to the access counter, and the sense amplifier performs a refresh operation of the memory cells connected to the activated word lines.

摘要翻译： 存储器可以包括：字线; 位线 存储器阵列块，包括存储器单元，每个存储器阵列块是数据读取操作或数据写入操作的单元; 行解码器，被配置为选择性地驱动所述字线; 配置成检测数据的感测放大器; 以及为每个存储器单元块提供的访问计数器，所述访问计数器对访问所述存储器阵列块的次数进行计数，以便读取数据或写入数据，以及当所述访问次数达到预定的次数时激活刷新请求信号 次数，其中在访问计数器的刷新请求信号的激活周期期间，行解码器周期性地并且顺序地激活对应于访问计数器的存储器阵列块的字线，并且读出放大器执行刷新操作 存储单元连接到激活的字线。

公开(公告)号：US06876588B2

公开(公告)日：2005-04-05

申请号：US10664464

申请日：2003-09-17

申请人： Daisuke Kato ,  Takashi Taira ,  Kenji Ishizuka ,  Yohji Watanabe ,  Munehiro Yoshida

发明人： Daisuke Kato ,  Takashi Taira ,  Kenji Ishizuka ,  Yohji Watanabe ,  Munehiro Yoshida

IPC分类号： G11C8/02 ,  G11C29/00 ,  G11C29/26 ,  G11C7/00

CPC分类号： G11C29/785 ,  G11C29/26 ,  G11C29/787 ,  G11C2029/2602

摘要： There is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a memory cell array are simultaneously activated. The semiconductor storage device includes an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not. The word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.