公开(公告)号：US20120094491A1

公开(公告)日：2012-04-19

申请号：US13376431

申请日：2010-08-16

申请人： Mamiko Kanamaru ,  Tomokazu Shimada ,  Takashi Shinoda

发明人： Mamiko Kanamaru ,  Tomokazu Shimada ,  Takashi Shinoda

IPC分类号： H01L21/306

CPC分类号： H01L21/3212 ,  C09G1/02 ,  C09K3/1463 ,  C09K3/1472

摘要： The invention relates to a CMP polishing liquid comprising a medium and silica particles as an abrasive grain dispersed into the medium, characterized in that: (A1) the silica particles have a silanol group density of 5.0/nm2 or less; (B1) a biaxial average primary particle diameter when arbitrary 20 silica particles are selected from an image obtained by scanning electron microscope observation is 25 to 55 nm; and (C1) an association degree of the silica particles is 1.1 or more. The invention provides a CMP polishing liquid which has the high barrier film polishing speed, the favorable abrasive grain dispersion stability, and the high interlayer dielectric polishing speed, and a polishing method producing semiconductor substrates or the like, that have excellent microfabrication, thin film formation, dimension accuracy, electric property and high reliability with low cost.

摘要翻译： 本发明涉及包含介质的CMP抛光液和分散在该介质中的磨粒的二氧化硅颗粒，其特征在于：（A1）二氧化硅颗粒的硅烷醇密度为5.0 / nm 2以下; （B1）当通过扫描电子显微镜观察获得的图像中选择20个二氧化硅颗粒时的双轴平均一次粒径为25〜55nm; 和（C1）二氧化硅颗粒的缔合度为1.1以上。 本发明提供了具有高阻隔膜研磨速度，良好的磨粒分散稳定性和高层间电介质抛光速度的CMP抛光液，以及制造半导体基板等的研磨方法，其具有优异的微细加工，薄膜形成 ，尺寸精度，电气性能和高可靠性，低成本。

公开(公告)号：US20110300778A1

公开(公告)日：2011-12-08

申请号：US13201518

申请日：2010-01-22

申请人： Hiroshi Ono ,  Takashi Shinoda ,  Yuuhei Okada

发明人： Hiroshi Ono ,  Takashi Shinoda ,  Yuuhei Okada

IPC分类号： B24B1/00 ,  C09K13/04

CPC分类号： H01L21/3212 ,  C09G1/02 ,  C09K3/1463 ,  H01L21/7684 ,  H01L21/76898

摘要： A polishing agent which comprises a composition containing an inorganic acid, an amino acid, a protective film-forming agent, an abrasive, an oxidizing agent, an organic acid and water, adjusted to a pH of 1.5-4, wherein the amount of potassium hydroxide required to raise the pH of the composition without the organic acid to 4 is at least 0.10 mol with respect to 1 kg of the composition without the organic acid, and the organic acid contains at least two carboxyl groups, wherein the logarithm of the inverse of the first acid dissociation constant (pKa1) is no greater than 3.

摘要翻译： 一种抛光剂，其包含调节至pH为1.5-4的无机酸，氨基酸，保护膜形成剂，研磨剂，氧化剂，有机酸和水的组合物，其中钾的量 相对于1kg不含有机酸的组合物，无机有机物将组合物的pH升高至4所需的氢氧化物为至少0.10mol，有机酸含有至少两个羧基，其中反相的对数 的第一个酸解离常数（pKa1）不大于3。

公开(公告)号：US20110027997A1

公开(公告)日：2011-02-03

申请号：US12937463

申请日：2009-04-16

申请人： Takashi Shinoda ,  Takaaki Tanaka ,  Mamiko Kanamaru ,  Jin Amanokura

发明人： Takashi Shinoda ,  Takaaki Tanaka ,  Mamiko Kanamaru ,  Jin Amanokura

IPC分类号： H01L21/302 ,  C09K3/14

CPC分类号： C09K3/1463 ,  B24B37/044 ,  C09G1/02 ,  H01L21/31053 ,  H01L21/3212

摘要： The present invention can provide a polishing liquid for CMP having good dispersion stability and a high polishing rate in polishing of interlayer insulating films and a polishing method. Disclosed a polishing liquid for CMP comprising: a medium; and colloidal silica particles dispersed in the medium, a blending amount of the colloidal silica particles being 2.0 to 8.0% by mass relative to 100% by mass of the polishing liquid, wherein the colloidal silica particles satisfy the following conditions (1) to (3): (1) a two-axis average primary particle diameter (R1) obtained from images of twenty arbitrarily selected colloidal silica particles observed by a scanning electron microscope is within the range of 35 to 55 nm; (2) a value S1/S0 obtained by dividing a specific surface area (S1) of a colloidal silica particle measured by BET method by a calculated specific surface area (S0) of a true sphere having the same particle diameter as the two-axis average primary particle diameter (R1) determined by (1) above is 1.20 or less; and (3) a ratio, association degree: RS/R1, of a secondary particle diameter (RS) of the colloidal silica particles measured with a dynamic light scattering particle size distribution analyzer and the two-axis average primary particle diameter (R1) determined by (1) above in the polishing liquid for CMP is 1.30 or less.

摘要翻译： 本发明可以提供一种用于CMP的抛光液，其具有在层间绝缘膜的研磨中具有良好的分散稳定性和高抛光速率以及抛光方法。 公开了一种用于CMP的抛光液，包括：介质; 和分散在该介质中的胶体二氧化硅粒子，相对于100质量％的研磨液，胶体二氧化硅粒子的配合量为2.0〜8.0质量％，其中胶态二氧化硅粒子满足下述条件（1）〜（3） ）：（1）通过扫描电子显微镜观察到的20个任意选择的胶体二氧化硅粒子的图像得到的2轴平均一次粒径（R1）在35〜55nm的范围内， （2）将通过BET法测定的胶体二氧化硅粒子的比表面积（S1）除以与两轴相同粒径的真球的计算比表面积（S0）得到的值S1 / S0 由（1）确定的平均一次粒径（R1）为1.20以下; 和（3）用动态光散射粒度分布分析仪测定的胶体二氧化硅粒子的二次粒径（RS）与双轴平均一次粒径（R1）的比例，相关度：RS / R1 在CMP抛光液中的（1）以上为1.30以下。

公开(公告)号：US20060134263A1

公开(公告)日：2006-06-22

申请号：US11280253

申请日：2005-11-17

申请人： Takashi Shinoda ,  Yoshimasa Makino

发明人： Takashi Shinoda ,  Yoshimasa Makino

IPC分类号： B29C45/03

CPC分类号： B29C45/53 ,  B29C45/17

摘要： In an injection device 10 having a plunger 11 reciprocably inserted into a heating cylinder 16, in which a molten material M is injected by the plunger 11 via a nozzle 21, a sealing portion 13 set so that the molten material M is prevented from easily entering a gap A between the plunger 11 and an inner wall 32 of the heating cylinder 16 is provided on the portion of the plunger 11, on the side of the nozzle 21, and the portion of the sealing portion 13, on the side of the nozzle 21 is a core keeping portion 14 provided so that an annular portion 20 which is formed on a front portion of the plunger 11 and is connected to a storage portion 19 of the molten material M is formed between the core keeping portion 14 and the inner wall 32 of the heating cylinder 16.

摘要翻译： 在具有往复插入到加热缸16中的柱塞11的注射装置10中，其中通过喷嘴21由柱塞11注入熔融材料M，密封部13被设定成使得熔融材料M被阻止容易地进入 柱塞11和加热缸16的内壁32之间的间隙A设置在柱塞11的喷嘴21侧，部分密封部13的喷嘴侧 图21所示的芯部保持部14被设置成使得形成在柱塞11的前部并连接到熔融材料M的容纳部分19的环形部分20形成在芯保持部分14和内壁 32。

公开(公告)号：US06850624B1

公开(公告)日：2005-02-01

申请号：US09517514

申请日：2000-03-02

申请人： Takashi Shinoda ,  Nobuharu Miura ,  Yoh Miyamoto

发明人： Takashi Shinoda ,  Nobuharu Miura ,  Yoh Miyamoto

IPC分类号： H04N1/387 ,  G06T1/00 ,  H04N1/32 ,  H04N1/46 ,  G06K9/00

CPC分类号： G06T1/0021 ,  G06T2201/0051 ,  G06T2201/0061 ,  H04N1/32309 ,  H04N1/32347

摘要： An intended image data structure is assumed to have a color information storing region and a pixel information storing region as its components. First, consider that the color information storing region within the image data structure is divided into a plurality of subregions, and a corresponding bit value is defined for each of the subregions. Next, an index number stored for each of pixels within the pixel information storing region is changed to an index number belonging to a subregion corresponding to a bit value of information to be embedded. In this way, one bit or more of information can be embedded for each pixel. Thus, a large amount of information can be embedded into a small-size image composed of simple shapes and having a small number of colors without degrading the image quality, and the information can be extracted from the image in which it has been embedded.

摘要翻译： 假设预期的图像数据结构具有颜色信息存储区域和像素信息存储区域作为其组件。 首先，考虑到图像数据结构内的颜色信息存储区域被划分为多个子区域，并且为每个子区域定义相应的位值。 接下来，将像素信息存储区域内的每个像素存储的索引号改变为属于与要嵌入的信息的位值相对应的子区域的索引号。 以这种方式，可以为每个像素嵌入一位或更多的信息。 因此，可以将大量的信息嵌入到由简单形状组成的小尺寸图像中并且具有少量颜色而不降低图像质量，并且可以从嵌入其中的图像中提取信息。

公开(公告)号：US5862095A

公开(公告)日：1999-01-19

申请号：US962351

申请日：1997-10-31

申请人： Yasushi Takahashi ,  Takashi Shinoda ,  Masamichi Ishihara ,  Tetsu Udagawa ,  Kazumasa Yanagisawa

发明人： Yasushi Takahashi ,  Takashi Shinoda ,  Masamichi Ishihara ,  Tetsu Udagawa ,  Kazumasa Yanagisawa

IPC分类号： G11C7/00 ,  G11C7/06 ,  G11C11/406

CPC分类号： G11C7/06 ,  G11C11/406

摘要： An ordinary read/write operation (normal operation) and a refresh operation are separated from one another and the number of read amplification circuits or in other words, the number of sense amplifiers operating during the normal operation is made smaller than that during the refresh operation. Accordingly, a bit line charge/discharge current during the normal operation can be reduced.

摘要翻译： 普通的读/写操作（正常操作）和刷新操作彼此分离，读取的放大电路的数量或换句话说，在正常操作期间操作的读出放大器的数量小于刷新操作期间的读出放大器的数量 。 因此，可以减少正常工作期间的位线充电/放电电流。

公开(公告)号：US5018109A

公开(公告)日：1991-05-21

申请号：US465890

申请日：1990-01-16

申请人： Takashi Shinoda ,  Masamichi Ishihara

发明人： Takashi Shinoda ,  Masamichi Ishihara

IPC分类号： G11C8/06

CPC分类号： G11C8/06

摘要： A microprocessor or the like supplies address signals for memory access according to its own operation speed irrespective of operation speed of a memory. A plurality of registers which take a plurality of address signals inputted in asynchronous state are installed in the memory. The memory access is performed according to sequence of the address signals taken in these plural registers.

摘要翻译： 无论存储器的操作速度如何，微处理器等都根据其自身的操作速度提供用于存储器访问的地址信号。 将多个以异步状态输入的地址信号的寄存器安装在存储器中。 根据在这些多个寄存器中取得的地址信号的顺序执行存储器访问。

公开(公告)号：US4839860A

公开(公告)日：1989-06-13

申请号：US820523

申请日：1986-01-17

申请人： Takashi Shinoda ,  Kikuo Sakai ,  Masahiro Ogata ,  Hiroshi Kawamoto ,  Yoshiaki Onishi, deceased ,  by Junko Onishi, administratrix

发明人： Takashi Shinoda ,  Kikuo Sakai ,  Masahiro Ogata ,  Hiroshi Kawamoto ,  Yoshiaki Onishi, deceased ,  by Junko Onishi, administratrix

IPC分类号： G06F11/10 ,  G11C17/08

CPC分类号： G06F11/1008 ,  G06F11/1076 ,  G11C17/08

摘要： A semiconductor memory includes a dummy cell for forming a reference potential, a read-only memory cell, and a differential amplifier circuit which receives the reference potential formed by the dummy cell and a signal read out from the memory cell. The differential amplifier circuit is dynamically operated so that the semiconductor memory is made smaller in power consumption and size than conventional units. Moreover, in order to reduce the power consumption, the memory cell is brought into the nonselection state when a predetermined time has passed after being selected. In addition, the semiconductor memory is provided with a compensating circuit in order to make the value of the capacitance connected to a word line for transmitting a selecting signal to the memory cell and the value of the capacitance connected to a dummy word line for transmitting a selecting signal to the dummy cell substantially equal to each other. Thus, the changes in potential of both the selecting signals are made substantially equal to each other. Accordingly, it is possible to reduce malfunctions.

摘要翻译： 半导体存储器包括用于形成参考电位的虚拟单元，只读存储单元和接收由虚设单元形成的参考电位的差分放大器电路和从存储单元读出的信号。 差分放大器电路是动态操作的，使得半导体存储器的功耗和尺寸比常规单元小。 此外，为了降低功耗，当选择了规定时间后，使存储单元变为非选择状态。 此外，半导体存储器设置有补偿电路，以便连接到用于将选择信号发送到存储单元的字线的电容的值和连接到用于发送选择信号的虚拟字线的电容的值 选择到虚拟单元的信号基本相等。 因此，使选择信号的电位变化大致相等。 因此，可以减少故障。

公开(公告)号：US4817052A

公开(公告)日：1989-03-28

申请号：US37048

申请日：1987-04-10

申请人： Takashi Shinoda ,  Osamu Sakai

发明人： Takashi Shinoda ,  Osamu Sakai

IPC分类号： G11C29/00 ,  G06F11/10 ,  G11C7/00 ,  G11C17/00 ,  G11C17/12 ,  G11C29/42 ,  G06F11/00

CPC分类号： G06F11/1008 ,  G06F11/1076 ,  G11C17/126

摘要： In a read only semiconductor memory, signal lines such as data lines are subjected to an undesired parasitic capacitance which restricts the signal changing rate along the lines. The parasitic capacitance which is driven by a memory cell will become increasingly higher as the memory capacity is increased. According to the present invention, a differential sense amplifier is used to amplify the data signals which are read out of the memory cell. At the same time, a dummy cell is used to generate a reference potential which is to be referred to by the differential sense amplifier. In particular, a dummy cell arrangement is provided wherein each dummy cell includes at least two series-connected semiconductor elements to provide a predetermined dummy cell conductance to establish a reference value. Another aspect of the invention lies in the use of column switches between a common data line and data lines of the memory arrays for coupling only one data line at a time through the column switch to the sense amplifier. In addition, a built-in error-correcting-code circuit is provided which operates in conjunction with a selecting circuit so that memory cells delivering a predetermined set of data are spaced apart from one another by at least predetermined distances to reduce the likelihood of errors from immediately adjacent memory cells.

摘要翻译： 在只读半导体存储器中，诸如数据线的信号线受到不期望的寄生电容的限制，沿着线路限制信号变化率。 随着存储器容量的增加，由存储器单元驱动的寄生电容将变得越来越高。 根据本发明，使用差分读出放大器来放大从存储单元读出的数据信号。 同时，使用虚拟单元来产生由差分读出放大器参考的参考电位。 特别地，提供了一种虚设单元布置，其中每个虚拟单元包括至少两个串联连接的半导体元件，以提供预定的虚设单元电导以建立参考值。 本发明的另一方面在于使用公共数据线和存储器阵列的数据线之间的列开关，用于仅通过列开关将一条数据线耦合到读出放大器。 此外，提供内置的纠错码电路，其与选择电路一起操作，使得传递预定数据集的存储器单元彼此间隔至少预定距离以减少错误的可能性 从紧邻的存储单元。

公开(公告)号：US4811295A

公开(公告)日：1989-03-07

申请号：US31425

申请日：1987-03-26

申请人： Takashi Shinoda

发明人： Takashi Shinoda

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/401 ,  G11C7/00

CPC分类号： G11C7/106 ,  G11C7/1033 ,  G11C7/1051

摘要： A pseudo static RAM having a function which enables high-speed serial read and write operations with a relatively simple circuit configuration. In the stage subsequent to an amplifier for amplifying read signals from memory cells which are output to complementary common data lines, there are provided a first flip-flop for transmitting the output signal from the amplifier to an output buffer in an ordinary read operation, a second flip-flop connected between the amplifier and the first flip-flop in a serial read operation so as to transmit the output signal from the amplifier to the output buffer in cooperation with the first flip-flop, and an address counter for successively selecting a plurality of data lines.

摘要翻译： 具有能够以比较简单的电路结构进行高速串行读写操作的功能的伪静态RAM。 在用于放大输出到互补公共数据线的存储器单元的读取信号的放大器之后的阶段中，提供了用于在普通读取操作中将来自放大器的输出信号发送到输出缓冲器的第一触发器， 第二触发器，其以串行读取操作连接在放大器和第一触发器之间，以便与第一触发器协作地将放大器的输出信号传输到输出缓冲器;以及地址计数器，用于连续选择 多条数据线。