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    Semiconductor memory having multiple continuous access functions
    7.
    发明授权
    Semiconductor memory having multiple continuous access functions 失效
    具有多个连续访问功能的半导体存储器

    公开(公告)号：US4802135A

    公开(公告)日：1989-01-31

    申请号：US902564

    申请日：1986-09-02

    申请人： Takashi Shinoda ,  Masamichi Ishihara

    发明人： Takashi Shinoda ,  Masamichi Ishihara

    IPC分类号： G11C11/34 ,  G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  G11C11/401 ,  G11C11/408 ,  G11C11/40 ,  G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/1021 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C8/18

    摘要： A pseudo static RAM is provided which uses a one MOSFET dynamic RAM cell, in which two functions of a page mode and a static column mode are realized by using an address buffer having a function to transmit address signals fed from external terminals as they are and a latch function to latch the address signals fed from the external terminals in synchronism with predetermined control signals fed from the external terminals. The address buffer also has a multiplexer function to selectively incorporate the address signals from the external terminals and the address signals produced in the inside of the RAM so that the address buffer and an internal address signal generating circuit may be controlled by external control terminals to make possible the continuous access by the internal address signals.

    摘要翻译： 提供了一种伪静态RAM，其使用一个MOSFET动态RAM单元，其中通过使用具有从外部端子原样馈送的地址信号的功能的地址缓冲器来实现页面模式和静态列模式的两个功能，以及 锁存功能，用于与从外部端子馈送的预定控制信号同步地锁存从外部端子馈送的地址信号。 地址缓冲器还具有多路复用功能，用于选择性地并入来自外部端子的地址信号和在RAM内部产生的地址信号，使得地址缓冲器和内部地址信号发生电路可以由外部控制端子控制， 可能通过内部地址信号的连续访问。

    Memory including address registers for increasing access speed to the memory
    8.
    发明授权
    Memory including address registers for increasing access speed to the memory 失效
    存储器包括用于增加存储器访问速度的地址寄存器

    公开(公告)号：US5018109A

    公开(公告)日：1991-05-21

    申请号：US465890

    申请日：1990-01-16

    申请人： Takashi Shinoda ,  Masamichi Ishihara

    发明人： Takashi Shinoda ,  Masamichi Ishihara

    IPC分类号： G11C8/06

    CPC分类号： G11C8/06

    摘要： A microprocessor or the like supplies address signals for memory access according to its own operation speed irrespective of operation speed of a memory. A plurality of registers which take a plurality of address signals inputted in asynchronous state are installed in the memory. The memory access is performed according to sequence of the address signals taken in these plural registers.

    摘要翻译： 无论存储器的操作速度如何，微处理器等都根据其自身的操作速度提供用于存储器访问的地址信号。 将多个以异步状态输入的地址信号的寄存器安装在存储器中。 根据在这些多个寄存器中取得的地址信号的顺序执行存储器访问。

    Memory including address registers
    9.
    发明授权
    Memory including address registers 失效
    存储器包括地址寄存器

    公开(公告)号：US4912679A

    公开(公告)日：1990-03-27

    申请号：US144066

    申请日：1988-01-15

    申请人： Takashi Shinoda ,  Masamichi Ishihara

    发明人： Takashi Shinoda ,  Masamichi Ishihara

    IPC分类号： G11C11/41 ,  G11C8/06

    CPC分类号： G11C8/06

    摘要： A microprocessor or the like supplies a plurality of address signals for memory access according to its own operation speed irrespective of the operation speed of a memory. A plurality of registers receives and stores the plurality of address signals which are inputted in an asynchronous state. The memory access is performed according to a sequence signals of the address signals stored in the plurality of registers.

    摘要翻译： 无论存储器的操作速度如何，微处理器等都根据其自身的操作速度提供用于存储器访问的多个地址信号。 多个寄存器接收并存储以异步状态输入的多个地址信号。 存储器访问根据存储在多个寄存器中的地址信号的序列信号进行。