公开(公告)号：US11139255B2

公开(公告)日：2021-10-05

申请号：US16411960

申请日：2019-05-14

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Denis Farison ,  Romain Coffy ,  Jean-Michel Riviere

IPC: H01L23/52 ,  H01L23/00 ,  H01L21/56 ,  H01L23/528 ,  H01L25/065 ,  H04L9/00

Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.

公开(公告)号：US10996412B2

公开(公告)日：2021-05-04

申请号：US16701355

申请日：2019-12-03

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Florian Perminjat ,  Romain Coffy ,  Jean-Michel Riviere

IPC: G02B6/43 ,  H05K1/02 ,  G02B6/12 ,  G02B6/42

Abstract: A carrier substrate includes a first network of electrical connections and recess. An electronic chip is mounted to the carrier substrate within the recess. The electronic chip includes an integrated guide of optical waves and a second network of electrical connections. A end section of an elongate optical cable is mounted on one side of the electronic chip with a longitudinal guide of optical waves optically coupled to the integrated guide of optical waves. Electrical connection elements are interposed between a face of the electronic chip and a bottom wall of the recess, such that first connect pads of the first electrical connection network are connected to second connect pads of the second electrical connection network through the electrical connection elements.

公开(公告)号：US10886210B2

公开(公告)日：2021-01-05

申请号：US16365063

申请日：2019-03-26

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Romain Coffy

IPC: H01L23/498 ,  H01L21/50 ,  H01L31/0203 ,  H01L23/10 ,  H01L23/31 ,  H01L23/00 ,  H01L23/58 ,  H05K5/02

Abstract: A cover for an electronic device includes a support body having a through-passage. An optical element which allows light to pass is mounted on said support body in a position extending across the through-passage. A surface of the optical element includes an electrically-conducting track configured as a security detection element. At least two electrical connection leads are rigidly attached to the support body and include first uncovered portions internal to the support body and electrically connected to spaced apart locations on the electrically-conducting track. The at least two electrical connection leads further including second uncovered portions external to said support body. The cover is mounted on a support plate carrying an electronic chip situated in the through-passage at a distance from the optical element.

公开(公告)号：US20130214425A1

公开(公告)日：2013-08-22

申请号：US13654850

申请日：2012-10-18

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Dominique Marais ,  Jacques Chavade ,  Rémi Brechignac ,  Eric Saugier ,  Romain Coffy ,  Luc Petit

IPC: H01L23/535

CPC classification number: H01L25/0652 ,  H01L23/3677 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0206 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/1053

Abstract: An electronic package includes a substrate wafer with an interconnect network. A first chip is fixed to a front of the substrate, connected to the interconnect network and encapsulated by a body. A second chip is placed on a back side of the substrate wafer and connected to the interconnect network by back-side connection elements interposed between the back side of the substrate and a front side of the second chip. Front-side connection elements are placed on the front side of the substrate and connected to the interconnect network. The connection elements extend beyond the frontal face of the body. The package may be mounted on a board with an interposed thermally conductive material.

Abstract translation: 电子封装包括具有互连网络的衬底晶片。 第一芯片固定到基板的前部，连接到互连网络并由主体封装。 第二芯片放置在基板晶片的背面，并通过设置在基板的背面和第二芯片的前侧之间的背面连接元件连接到互连网络。 前端连接元件放置在基板的正面并连接到互连网络。 连接元件延伸超出身体的正面。 封装可以安装在具有插入的导热材料的板上。

公开(公告)号：US20130079068A1

公开(公告)日：2013-03-28

申请号：US13629872

申请日：2012-09-28

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Romain Coffy ,  Julien Vittu

IPC: H01L27/14 ,  H04W88/02

CPC classification number: H01L25/167 ,  G01S7/4813 ,  G01S17/026 ,  H01L31/0203 ,  H01L31/02325 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A package includes a substrate with an attached emitting IC chip and receiving IC chip. The emitting IC chip includes an optical emitter, and the receiving IC chip includes a main optical sensor and a secondary optical sensor. A case is provided with a bottom portion and a peripheral wall portion to cover the IC chips, wherein the edge of the peripheral wall portion is mounted to the substrate. The bottom portion of the case includes a main opening above the main optical sensor and a secondary opening above the optical emitter. An opaque material is interposed between the case and the receiving IC chip to isolate the main optical sensor from the secondary optical sensor and delimiting a chamber containing the secondary optical sensor and the optical emitter. The chamber is optically isolated from the main optical sensor and main opening, and may be filled with a transparent material.

Abstract translation: 封装包括具有附接的发射IC芯片并接收IC芯片的基板。 发光IC芯片包括光发射器，并且接收IC芯片包括主光学传感器和次级光学传感器。 壳体设置有覆盖IC芯片的底部部分和周壁部分，其中周壁部分的边缘安装到基板。 壳体的底部包括在主光学传感器上方的主开口和在光发射器上方的次级开口。 在外壳和接收IC芯片之间插入不透明材料，以将主光学传感器与次级光学传感器隔离，并且限定包含第二光学传感器和光学发射器的室。 该室与主光学传感器和主开口光学隔离，并且可以填充有透明材料。