公开(公告)号：US20150262941A1

公开(公告)日：2015-09-17

申请号：US14640237

申请日：2015-03-06

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Francis Steffen ,  Delphine Mathey ,  Gilbert Assaud ,  Rémi Brechignac

IPC: H01L23/00 ,  H01L21/311 ,  H01L23/522 ,  H01L23/31 ,  H01L23/04

CPC classification number: H01L23/562 ,  H01L21/31105 ,  H01L21/565 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/522 ,  H01L23/57 ,  H01L23/573 ,  H01L24/32 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic package includes an integrated circuit chip mounted to a support plate and encapsulated by an encapsulating body. The package includes at least one weakening deep perforation. The perforation is formed in either the support plate or the encapsulating body, and functions to reduce a resistance of the package to bending stresses perpendicular to the support plate.

Abstract translation: 电子封装包括安装到支撑板并由封装体封装的集成电路芯片。 该包装包括至少一个削弱的深穿孔。 穿孔形成在支撑板或封装体中，并且用于减小包装件垂直于支撑板的弯曲应力的阻力。

公开(公告)号：US09196590B2

公开(公告)日：2015-11-24

申请号：US14640237

申请日：2015-03-06

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Francis Steffen ,  Delphine Mathey ,  Gilbert Assaud ,  Rémi Brechignac

IPC: H01L23/28 ,  H01L23/00 ,  H01L23/31 ,  H01L23/04 ,  H01L23/522 ,  H01L21/311 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/31105 ,  H01L21/565 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/522 ,  H01L23/57 ,  H01L23/573 ,  H01L24/32 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic package includes an integrated circuit chip mounted to a support plate and encapsulated by an encapsulating body. The package includes at least one weakening deep perforation. The perforation is formed in either the support plate or the encapsulating body, and functions to reduce a resistance of the package to bending stresses perpendicular to the support plate.

Abstract translation: 电子封装包括安装到支撑板并由封装体封装的集成电路芯片。 该包装包括至少一个削弱的深穿孔。 穿孔形成在支撑板或封装体中，并且用于减小包装件垂直于支撑板的弯曲应力的阻力。

公开(公告)号：US09076749B2

公开(公告)日：2015-07-07

申请号：US14512060

申请日：2014-10-10

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Romain Coffy ,  Rémi Brechignac

IPC: H01L23/02 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H01L23/522 ,  H01L25/18

CPC classification number: H01L24/33 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5226 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/32146 ,  H01L2224/32225 ,  H01L2224/32235 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/144 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An electronic system includes a first integrated-circuit chip and a second integrated-circuit chip. A first substrate wafer is positioned between the first and second integrated-circuit chips and configured with a first connection network to make electrical connection to the first integrated-circuit chip. A second substrate wafer, configured with a second connection network to make electrical connection to the second integrated-circuit chip, is positioned facing the first substrate wafer. The connection networks of the first and second substrate wafers are electrically connected through connection structures. A third substrate wafer, including a third connection network, is thermally in contact with the first integrated-circuit chip and electrically connected to the first connection network of the first substrate wafer through further connection structures. The further connection structure may be formed using another substrate wafer.

Abstract translation: 电子系统包括第一集成电路芯片和第二集成电路芯片。 第一衬底晶片位于第一和第二集成电路芯片之间并且配置有第一连接网络以与第一集成电路芯片进行电连接。 配置有与第二集成电路芯片进行电连接的第二连接网络的第二衬底晶片被定位成面向第一衬底晶片。 第一和第二衬底晶片的连接网络通过连接结构电连接。 包括第三连接网络的第三衬底晶片与第一集成电路芯片热接触，并通过另外的连接结构电连接到第一衬底晶片的第一连接网络。 另外的连接结构可以使用另一个衬底晶片形成。

公开(公告)号：US20150102500A1

公开(公告)日：2015-04-16

申请号：US14512060

申请日：2014-10-10

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Romain Coffy ,  Rémi Brechignac

IPC: H01L23/00 ,  H01L23/522

CPC classification number: H01L24/33 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5226 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/32146 ,  H01L2224/32225 ,  H01L2224/32235 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/144 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An electronic system includes a first integrated-circuit chip and a second integrated-circuit chip. A first substrate wafer is positioned between the first and second integrated-circuit chips and configured with a first connection network to make electrical connection to the first integrated-circuit chip. A second substrate wafer, configured with a second connection network to make electrical connection to the second integrated-circuit chip, is positioned facing the first substrate wafer. The connection networks of the first and second substrate wafers are electrically connected through connection structures. A third substrate wafer, including a third connection network, is thermally in contact with the first integrated-circuit chip and electrically connected to the first connection network of the first substrate wafer through further connection structures. The further connection structure may be formed using another substrate wafer.

Abstract translation: 电子系统包括第一集成电路芯片和第二集成电路芯片。 第一衬底晶片位于第一和第二集成电路芯片之间并且配置有第一连接网络以与第一集成电路芯片进行电连接。 配置有与第二集成电路芯片进行电连接的第二连接网络的第二衬底晶片被定位成面向第一衬底晶片。 第一和第二衬底晶片的连接网络通过连接结构电连接。 包括第三连接网络的第三衬底晶片与第一集成电路芯片热接触，并通过另外的连接结构电连接到第一衬底晶片的第一连接网络。 另外的连接结构可以使用另一个衬底晶片形成。

公开(公告)号：US09006904B2

公开(公告)日：2015-04-14

申请号：US13654850

申请日：2012-10-18

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Dominique Marais ,  Jacques Chavade ,  Rémi Brechignac ,  Eric Saugier ,  Romain Coffy ,  Luc Petit

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/367 ,  H01L25/065 ,  H05K1/02 ,  H05K3/34

CPC classification number: H01L25/0652 ,  H01L23/3677 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0206 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/1053

Abstract: An electronic package includes a substrate wafer with an interconnect network. A first chip is fixed to a front of the substrate, connected to the interconnect network and encapsulated by a body. A second chip is placed on a back side of the substrate wafer and connected to the interconnect network by back-side connection elements interposed between the back side of the substrate and a front side of the second chip. Front-side connection elements are placed on the front side of the substrate and connected to the interconnect network. The connection elements extend beyond the frontal face of the body. The package may be mounted on a board with an interposed thermally conductive material.

Abstract translation: 电子封装包括具有互连网络的衬底晶片。 第一芯片固定到基板的前部，连接到互连网络并由主体封装。 第二芯片放置在基板晶片的背面，并通过设置在基板的背面和第二芯片的前侧之间的背面连接元件连接到互连网络。 前端连接元件放置在基板的正面并连接到互连网络。 连接元件延伸超出身体的正面。 封装可以安装在具有插入的导热材料的板上。

公开(公告)号：US20130214425A1

公开(公告)日：2013-08-22

申请号：US13654850

申请日：2012-10-18

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Dominique Marais ,  Jacques Chavade ,  Rémi Brechignac ,  Eric Saugier ,  Romain Coffy ,  Luc Petit

IPC: H01L23/535

CPC classification number: H01L25/0652 ,  H01L23/3677 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0206 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/1053

Abstract: An electronic package includes a substrate wafer with an interconnect network. A first chip is fixed to a front of the substrate, connected to the interconnect network and encapsulated by a body. A second chip is placed on a back side of the substrate wafer and connected to the interconnect network by back-side connection elements interposed between the back side of the substrate and a front side of the second chip. Front-side connection elements are placed on the front side of the substrate and connected to the interconnect network. The connection elements extend beyond the frontal face of the body. The package may be mounted on a board with an interposed thermally conductive material.

Abstract translation: 电子封装包括具有互连网络的衬底晶片。 第一芯片固定到基板的前部，连接到互连网络并由主体封装。 第二芯片放置在基板晶片的背面，并通过设置在基板的背面和第二芯片的前侧之间的背面连接元件连接到互连网络。 前端连接元件放置在基板的正面并连接到互连网络。 连接元件延伸超出身体的正面。 封装可以安装在具有插入的导热材料的板上。