公开(公告)号：US09691860B2

公开(公告)日：2017-06-27

申请号：US14698817

申请日：2015-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Rwik Sengupta

IPC: H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/165 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/1054 ,  H01L29/66 ,  H01L29/66795

Abstract: A strain-relieved buffer is formed by forming a first silicon-germanium (SiGe) layer directly on a surface of a bulk silicon (Si) substrate. The first SiGe layer is patterned to form at least two SiGe structures so there is a space between the SiGe structures. An oxide is formed on the SiGe structures, and the SiGe structures are mesa annealed. The oxide is removed to expose a top portion of the SiGe structures. A second SiGe layer is formed on the exposed portion of the SiGe structures so that the second SiGe layer covers the space between the SiGe structures, and so that a percentage Ge content of the first and second SiGe layers are substantially equal. The space between the SiGe structures is related to the sizes of the structures adjacent to the space and an amount of stress relief that is associated with the structures.

公开(公告)号：US20170040209A1

公开(公告)日：2017-02-09

申请号：US15066177

申请日：2016-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark Rodder ,  Borna Obradovic

IPC: H01L21/762 ,  H01L21/322 ,  H01L21/306 ,  H01L21/311

CPC classification number: H01L21/76251 ,  H01L21/02002 ,  H01L21/306 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/3226

Abstract: Methods of forming nanosheets for a semiconductor device are provided including providing a silicon on insulator (SOI) handle wafer, the SOT handle wafer including a silicon layer and a dielectric layer on the silicon layer; providing a first donor wafer; bonding the SOI handle wafer and the first donor wafer together to provide a bonded structure; debonding the bonded structure to provide an intermediate wafer including a plurality of silicon or non-silicon nano sheets and a plurality of dielectric layers alternately stacked; and bonding the intermediate wafer to a second donor wafer to provide a final wafer including a plurality of silicon or non-silicon layers and a plurality of dielectric layers alternately stacked, wherein the final wafer includes at least one more pair of silicon or non-silicon and dielectric layers than the intermediate wafer.

Abstract translation: 提供了形成半导体器件的纳米片的方法，包括提供绝缘体上硅（SOI）处理晶片，SOT处理晶片在硅层上包括硅层和介电层; 提供第一施主晶片; 将SOI处理晶片和第一施主晶片结合在一起以提供结合结构; 剥离粘合结构以提供包括交替层叠的多个硅或非硅纳米片和多个电介质层的中间晶片; 以及将所述中间晶片接合到第二施主晶片以提供包括交替层叠的多个硅或非硅层和多个电介质层的最终晶片，其中所述最终晶片包括至少一对硅或非硅 和电介质层比中间晶片。

公开(公告)号：US20160071729A1

公开(公告)日：2016-03-10

申请号：US14830622

申请日：2015-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Robert C. Bowen ,  Wei-E Wang ,  Mark S. Rodder

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/1033 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02474 ,  H01L21/02477 ,  H01L21/02483 ,  H01L21/02485 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/02538 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/78654 ,  H01L29/78696

Abstract: Exemplary embodiments provide methods for fabricating a nanosheet structure suitable for field-effect transistor (FET) fabrication. Aspects of exemplary embodiment include selecting an active material that will serve as a channel material in the nanosheet structure, a substrate suitable for epitaxial growth of the active material, and a sacrificial material to be used during fabrication of the nanosheet structure; growing a stack of alternating layers of active and sacrificial materials over the substrate; and selectively etching the sacrificial material, wherein due to the properties of the sacrificial material, the selective etch results in remaining layers of active material having an aspect ratio greater than 1 and substantially a same thickness and atomic smoothness along the entire cross-sectional width of each active material layer perpendicular to current flow.

Abstract translation: 示例性实施例提供了制造适用于场效应晶体管（FET）制造的纳米片结构的方法。 示例性实施方案的方面包括选择将用作纳米片结构中的通道材料的活性材料，适于活性材料的外延生长的基底和在纳米片结构的制造期间使用的牺牲材料; 在衬底上生长一叠交替的活性和牺牲材料层; 并且选择性地蚀刻牺牲材料，其中由于牺牲材料的性质，选择性蚀刻导致活性材料的剩余层具有大于1的纵横比和基本上相同的厚度和原子平滑度沿着整个横截面宽度 每个活性物质层垂直于电流。