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    INTEGRATED CIRCUIT DEVICES INCLUDING SOURCE/DRAIN EXTENSION REGIONS AND METHODS OF FORMING THE SAME
    4.
    发明申请
    INTEGRATED CIRCUIT DEVICES INCLUDING SOURCE/DRAIN EXTENSION REGIONS AND METHODS OF FORMING THE SAME 有权
    集成电路设备，包括源/漏电延伸区域及其形成方法

    公开(公告)号：US20160172358A1

    公开(公告)日：2016-06-16

    申请号：US14961005

    申请日：2015-12-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ryan M. Hatcher ,  Borna J. Obradovic

    IPC: H01L27/088 ,  H01L29/423

    CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7833 ,  H01L29/78696

    Abstract: Integrated circuit devices may include a stack that includes channel regions and gate electrodes stacked in an alternating sequence in a vertical direction. The channel regions may include impurities having a first conductivity type. The integrated circuit devices may also include source/drain regions on respective opposing sides of the stack, and the source/drain regions may be spaced apart from each other in a horizontal direction and may include impurities having a second conductivity type that is different from the first conductivity type. The integrated circuit devices may further include extension regions that may be between respective ones of channel regions and one of the source/drain regions and may include impurities having the second conductivity type. Each of the extension regions may have a thickness in the vertical direction that is less than those of the channel regions and the one of the source/drain regions.

    Abstract translation: 集成电路器件可以包括堆叠，其包括在垂直方向上以交替顺序堆叠的沟道区和栅电极。 沟道区可以包括具有第一导电类型的杂质。 集成电路器件还可以包括堆叠的相应相对侧上的源极/漏极区域，并且源极/漏极区域可以在水平方向上彼此间隔开，并且可以包括具有与第二导电类型不同的第二导电类型的杂质 第一导电类型。 集成电路器件还可以包括可以在相应的沟道区和源极/漏极区之一之间的延伸区域，并且可以包括具有第二导电类型的杂质。 每个延伸区域可以具有比沟道区域和源极/漏极区域中的一个小的垂直方向上的厚度。

    STRAINED STACKED NANOSHEET FETS AND/OR QUANTUM WELL STACKED NANOSHEET
    5.
    发明申请
    STRAINED STACKED NANOSHEET FETS AND/OR QUANTUM WELL STACKED NANOSHEET 有权
    应变堆叠的纳米晶体管和/或量子堆积的纳米硅片

    公开(公告)号：US20160111337A1

    公开(公告)日：2016-04-21

    申请号：US14887484

    申请日：2015-10-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ryan M. Hatcher ,  Robert C. Bowen ,  Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong

    IPC: H01L21/8238 ,  H01L21/306 ,  H01L29/78 ,  H01L21/02

    CPC classification number: H01L21/823807 ,  H01L21/823828 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/22 ,  H01L29/42392 ,  H01L29/66484 ,  H01L29/775 ,  H01L29/7847

    Abstract: Exemplary embodiments provide for fabricating a biaxially strained nanosheet. Aspects of the exemplary embodiments include: growing an epitaxial crystalline initial superlattice having one or more periods, each of the periods comprising at least three layers, an active material layer, a first sacrificial material layer and a second sacrificial material layer, the first and second sacrificial material layers having different material properties; in each of the one or more periods, placing each of the active material layers between the first and second sacrificial material layers, wherein lattice constants of the first and second sacrificial material layers are different than the active material layer and impose biaxial stress in the active material layer; selectively etching away all of the first sacrificial material layers thereby exposing one surface of the active material for additional processing, while the biaxial strain in the active material layers is maintained by the second sacrificial material layers; and selectively etching away all of the second sacrificial material layers thereby exposing a second surface of the active material layers for additional processing.

    Abstract translation: 示例性实施例提供制造双轴应变纳米片。 示例性实施例的方面包括：生长具有一个或多个周期的外延晶体初始超晶格，每个周期包括至少三个层，活性材料层，第一牺牲材料层和第二牺牲材料层，第一和第二 具有不同材料特性的牺牲材料层; 在一个或多个周期的每一个中，将每个活性材料层放置在第一和第二牺牲材料层之间，其中第一和第二牺牲材料层的晶格常数不同于活性材料层并且在活性物质层中施加双轴应力 材料层; 选择性地蚀刻掉所有的第一牺牲材料层，从而暴露活性材料的一个表面以进行附加处理，同时活性材料层中的双轴应变由第二牺牲材料层保持; 并且选择性地蚀刻掉所有第二牺牲材料层，从而暴露活性材料层的第二表面用于额外的处理。

    Bi-directional weight cell
    7.
    发明授权
    Bi-directional weight cell 有权

    公开(公告)号：US10739186B2

    公开(公告)日：2020-08-11

    申请号：US15886753

    申请日：2018-02-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ryan M. Hatcher ,  Jorge A. Kittl ,  Borna J. Obradovic ,  Titash Rakshit

    IPC: G11C7/10 ,  G11C13/00 ,  G01G23/38 ,  G06G7/16 ,  G11C11/54 ,  G06N3/063 ,  G11C11/16

    Abstract: A weight cell including first and second bi-directional memory elements each configured to switch between a first resistance state and a second resistance state different than the first resistance state. A first input line is connected to a first terminal of the first bi-directional memory element, and a second input line is connected to the first terminal of the second bi-directional memory element. A first diode in forward bias connects the second terminal of the first bi-directional memory element to a first output line, a second diode in reverse bias connects the second terminal of the second bi-directional memory element to a second output line, a third diode in reverse bias connects the second terminal of the first bi-directional memory element to the second output line, and a fourth diode in forward bias connects the second terminal of the second bi-directional memory element to the first output line.

    MEMORY DEVICE WITH STRONG POLARIZATION COUPLING
    9.
    发明申请
    MEMORY DEVICE WITH STRONG POLARIZATION COUPLING 审中-公开

    公开(公告)号：US20190318774A1

    公开(公告)日：2019-10-17

    申请号：US16142944

    申请日：2018-09-26

    Applicant: Samsung Electronics Co., LTD.

    Inventor： Jorge A. Kittl ,  Borna J. Obradovic ,  Ryan M. Hatcher ,  Titash Rakshit

    IPC: G11C11/22

    Abstract: A semiconductor memory device and method for providing the semiconductor memory device are described. The semiconductor memory device includes a ferroelectric capacitor. The ferroelectric capacitor includes a first electrode, a second electrode and a multilayer insulator structure between the first and second electrodes. The multilayer insulator structure includes at least one ferroelectric layer and at least one dielectric layer. The at least one ferroelectric layer and the at least one dielectric layer share at least one interface and have a strong polarization coupling.

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