公开(公告)号：US07176530B1

公开(公告)日：2007-02-13

申请号：US10803203

申请日：2004-03-17

Applicant: Constantin Bulucea ,  Philipp Lindorfer

Inventor： Constantin Bulucea ,  Philipp Lindorfer

IPC: H01L29/76

CPC classification number: H01L21/823807 ,  H01L21/26586 ,  H01L27/0883 ,  H01L27/0928 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/665 ,  H01L29/7833

Abstract: A semiconductor technology combines a normally off n-channel channel-junction insulated-gate field-effect transistor (“IGFET”) (104) and an n-channel surface-channel IGFET (100 or 160) to reduce low-frequency 1/f noise. The channel-junction IGFET is normally of materially greater gate dielectric thickness than the surface-channel IGFET so as to operate across a greater voltage range than the surface-channel IGFET. Alternatively or additionally, the channel-junction IGFET may conduct current through a field-induced surface channel. A p-channel surface-channel IGFET (102 or 162), which is typically of approximately the same gate-dielectric thickness as the n-channel surface-channel IGFET, is preferably combined with the two n-channel IGFETs to produce a complementary-IGFET structure. A further p-channel IGFET (106, 180, 184, or 192), which is typically of approximately the same gate dielectric thickness as the n-channel channel-junction IGFET, is also preferably included. The further p-channel IGFET can be a surface-channel or channel-junction device.

Abstract translation: 半导体技术结合了正常n沟道沟道结绝缘栅场效应晶体管（“IGFET”）（104）和n沟道表面沟道IGFET（100或160），以降低低频1 / f 噪声。 沟道结IGFET通常具有比表面沟道IGFET大得多的栅介质厚度，以便在比表面沟道IGFET更大的电压范围内工作。 或者或另外，通道结IGFET可以传导电流通过场诱导的表面通道。 通常与n沟道表面沟道IGFET大致相同的栅介质厚度的p沟道表面沟道IGFET（102或162）优选与两个n沟道IGFET组合， IGFET结构。 还优选包括通常具有与n沟道沟道结IGFET大致相同的栅介质厚度的另外的p沟道IGFET（106,180,184或192）。 另外的p沟道IGFET可以是表面沟道或沟道结器件。

公开(公告)号：US06797576B1

公开(公告)日：2004-09-28

申请号：US10327352

申请日：2002-12-20

Applicant: Chih Sieh Teng ,  Constantin Bulucea ,  Chin-Miin Shyu ,  Fu-Cheng Wang ,  Prasad Chaparala

Inventor： Chih Sieh Teng ,  Constantin Bulucea ,  Chin-Miin Shyu ,  Fu-Cheng Wang ,  Prasad Chaparala

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/665

Abstract: An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &mgr;m deep into the body material but not more than 0.1 &mgr;m deep into the body material. The source/drain zones (140 and 142 or 160 and 162) of a p-channel IGFET (120 or 122) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed.

Abstract translation: IGFET（40或42）具有位于主体材料（50）中的通道区（64或84）。 通过设置通道区域中的净掺杂剂浓度以在IGFET的源极/漏极区域（60和62或80和82）之间的位置处纵向达到局部表面最小值来减轻短通道阈值电压滚降和穿透，以及 通过布置主体材料中的净掺杂剂浓度达到主体材料深度超过0.1μm的局部地下最大深度，但不超过0.1μm深的主体材料。 p沟道IGFET（120或122）的源极/漏极区（140和142或160和162）具有渐变结特征以减小结电容，从而提高开关速度。

公开(公告)号：US06627950B1

公开(公告)日：2003-09-30

申请号：US08851608

申请日：1997-05-05

Applicant: Constantin Bulucea ,  Rebecca Rossen

Inventor： Constantin Bulucea ,  Rebecca Rossen

IPC: H01L2976

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/7811 ,  Y10S148/126

Abstract: Power MOSFET apparatus, and method for its production, that suppresses voltage breakdown near the gate, using a polygon-shaped trench in which the gate is positioned, using a shaped deep body junction that partly lies below the trench bottom, and using special procedures for growth of gate oxide at various trench corners.

Abstract translation: 功率MOSFET器件及其制造方法，使用位于沟槽底部下方的成形深体结，使用位于栅极的多边形沟槽来抑制栅极附近的电压击穿，并使用特殊程序 栅极氧化物在各种沟角处的生长。

公开(公告)号：US06576966B1

公开(公告)日：2003-06-10

申请号：US09535434

申请日：2000-03-23

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L2976

CPC classification number: H01L29/66659 ,  H01L21/823807 ,  H01L27/0928 ,  H01L29/1045 ,  H01L29/7835

Abstract: An asymmetric insulated-gate field-effect transistor (40) is configured in an asymmetric lightly doped drain structure that alleviates hot-carrier effects and enables the source characteristics to be decoupled from the drain characteristics. The transistor has a multi-part channel formed with an output portion (46), which adjoins the drain zone, and a more heavily doped input portion (42), which adjoins the source zone (44). The drain zone contains a main portion (52) and a more lightly doped extension (50) that meets the output channel portion. The drain extension extends at least as far below the upper semiconductor surface as the main drain portion so as to help reduce hot-carrier effects. The input channel portion is situated in a threshold body zone (53) whose doping determines the threshold voltage. The provision of a lightly doped source extension is avoided so that improving the drain characteristics does not harm the source characteristics, and vice versa.

Abstract translation: 非对称绝缘栅场效应晶体管（40）配置在不对称轻掺杂漏极结构中，其减轻热载流子效应，并使得源极特性能够与漏极特性去耦合。 晶体管具有形成有与漏极区相邻的输出部分（46）和与源区（44）相邻的更重掺杂的输入部分（42）的多部分通道。 漏区包含与输出通道部分相遇的主要部分（52）和更轻掺杂的延伸部（50）。 漏极延伸部至少与主漏极部分的上半导体表面一样远，以帮助减少热载流子效应。 输入通道部分位于阈值体区（53）中，其掺杂决定了阈值电压。 避免提供轻掺杂的源延伸，从而改善漏极特性不会损害源特性，反之亦然。

公开(公告)号：US5441900A

公开(公告)日：1995-08-15

申请号：US308698

申请日：1994-09-19

Applicant: Constantin Bulucea ,  Esin Dermirlioglu ,  Sheldon Aronowitz

Inventor： Constantin Bulucea ,  Esin Dermirlioglu ,  Sheldon Aronowitz

IPC: H01L27/092 ,  H01L21/265

CPC classification number: H01L27/0921 ,  Y10S148/023 ,  Y10S438/904 ,  Y10S438/917

Abstract: A unique approach to suppressing latchup in CMOS structures is described. Atomic species that exhibit midgap levels in silicon and satisfy the criteria for localized action and electrical compatibility can be implanted to suppress the parasitic bipolar behavior which causes latchup. Reduction of minority carrier lifetime can be achieved in critical parasitic bipolar regions that, by CMOS construction are outside the regions of active MOS devices. One way to accomplish this goal is to use the source/drain masks to locally implant the minority carrier lifetime reducer (MCLR) before the source/drain dopants are implanted. This permits the MCLR to be introduced at different depths or even to be different species, of the n and p-channel transistors. Another way to accomplish this goal requires that a blanket MCLR implant be done very early in the process, before isolation oxidation, gate oxidation or active threshold implants are done.

Abstract translation: 描述了抑制CMOS结构中的闭锁的独特方法。 可以植入在硅中显示中间水平并满足局部作用和电相容性标准的原子物质，以抑制引起闭锁的寄生双极性行为。 通过CMOS结构在有源MOS器件区域之外的临界寄生双极区域可以实现少数载流子寿命的降低。 实现这一目标的一个方法是在源极/漏极掺杂剂被植入之前，使用源极/漏极掩模来局部注入少数载流子寿命衰减器（MCLR）。 这允许MCLR在n沟道晶体管和p沟道晶体管的不同深度或者甚至不同的物种中被引入。 实现这一目标的另一种方法是要求在隔离氧化，栅极氧化或活性阈值植入完成之前，在该过程中非常早地完成覆盖MCLR植入物。

公开(公告)号：US08610207B2

公开(公告)日：2013-12-17

申请号：US13298283

申请日：2011-11-16

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L21/8238

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

Abstract: An insulated-gate field-effect transistor (220U) utilizes an empty-well region for achieving high performance. The concentration of the body dopant reaches a maximum at a subsurface location no more than 10 times deeper below the upper semiconductor surface than the depth of one of a pair of source/drain zones (262 and 264), decreases by at least a factor of 10 in moving from the subsurface location along a selected vertical line (136U) through that source/drain zone to the upper semiconductor surface, and has a logarithm that decreases substantially monotonically and substantially inflectionlessly in moving from the subsurface location along the vertical line to that source/drain zone. Each source/drain zone has a main portion (262M or 264M) and a more lightly doped lateral extension (262E or 264E). Alternatively or additionally, a more heavily doped pocket portion (280) of the body material extends along one of the source/drain zones.

Abstract translation: 绝缘栅场效应晶体管（220U）利用空阱区实现高性能。 身体掺杂物的浓度在上半导体表面下方比在一对源/漏区（262和264）之一的深度不超过10倍的地下位置处达到最大值，减小至少一个因子 10沿着沿着选择的垂直线（136U）通过该源极/漏极区域移动到上半导体表面的地下位置移动，并且具有从沿着垂直线的地下位置移动到基本单调和基本上无穷地减小的对数， 源/漏区。 每个源/漏区具有主要部分（262M或264M）和更轻掺杂的横向延伸（262E或264E）。 替代地或另外地，主体材料的更重掺杂的凹穴部分（280）沿着源极/漏极区域中的一个延伸。

公开(公告)号：US20130126983A1

公开(公告)日：2013-05-23

申请号：US13298283

申请日：2011-11-16

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L29/78

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

Abstract: An insulated-gate field-effect transistor (220U) utilizes an empty-well region for achieving high performance. The concentration of the body dopant reaches a maximum at a subsurface location no more than 10 times deeper below the upper semiconductor surface than the depth of one of a pair of source/drain zones (262 and 264), decreases by at least a factor of 10 in moving from the subsurface location along a selected vertical line (136U) through that source/drain zone to the upper semiconductor surface, and has a logarithm that decreases substantially monotonically and substantially inflectionlessly in moving from the subsurface location along the vertical line to that source/drain zone. Each source/drain zone has a main portion (262M or 264M) and a more lightly doped lateral extension (262E or 264E). Alternatively or additionally, a more heavily doped pocket portion (280) of the body material extends along one of the source/drain zones.

Abstract translation: 绝缘栅场效应晶体管（220U）利用空阱区实现高性能。 身体掺杂物的浓度在上半导体表面下方比在一对源/漏区（262和264）之一的深度不超过10倍的地下位置处达到最大值，减小至少一个因子 10沿着沿着选择的垂直线（136U）通过该源极/漏极区域移动到上半导体表面的地下位置移动，并且具有从沿着垂直线的地下位置移动到基本单调和基本上无穷地减小的对数， 源/漏区。 每个源/漏区具有主要部分（262M或264M）和更轻掺杂的横向延伸（262E或264E）。 替代地或另外地，主体材料的更重掺杂的凹穴部分（280）沿着源极/漏极区域中的一个延伸。

公开(公告)号：US08304835B2

公开(公告)日：2012-11-06

申请号：US12382973

申请日：2009-03-27

Applicant: Constantin Bulucea ,  Sandeep R. Bahl ,  William D. French ,  Jeng-Jiun Yang ,  Donald M. Archer ,  D. Courtney Parker ,  Prasad Chaparala

Inventor： Constantin Bulucea ,  Sandeep R. Bahl ,  William D. French ,  Jeng-Jiun Yang ,  Donald M. Archer ,  D. Courtney Parker ,  Prasad Chaparala

IPC: H01L29/36

CPC classification number: H01L27/088 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (100, 102, 112, 114, 124, and 126) utilize empty wells (180, 182, 192, 194, 204, and 206) in achieving desired transistor characteristics. Other IGFETs (108, 110, 116, 118, 120, and 122) utilize filled wells (188, 190, 196, 198, 200, and 202) in achieving desired transistor characteristics. The combination of empty and filled wells enables the semiconductor fabrication platform to provide a wide variety of high-performance IGFETs from which circuit designers can select particular IGFETs for various analog and digital applications, including mixed-signal applications.

Abstract translation: 作为半导体制造平台的核心的半导体结构具有由电子元件特别是绝缘栅场效应晶体管（IGFET）不同地使用的空阱区域和填充阱区域的组合，以实现期望的电子 特点 相当少量的半导体阱掺杂剂靠近空穴的顶部。 相当数量的半导体阱掺杂剂靠近填充井的顶部。 一些IGFET（100,102,112,114,124和126）利用空井（180,182,192,194,204和206）实现期望的晶体管特性。 其它IGFET（108,110,116,118,120和122）利用填充的孔（188,190,196,198,200和202）实现期望的晶体管特性。 空孔和填充孔的组合使得半导体制造平台能够提供各种各样的高性能IGFET，电路设计者可以从其中选择特定的IGFET用于各种模拟和数字应用，包括混合信号应用。

公开(公告)号：US08304308B2

公开(公告)日：2012-11-06

申请号：US13198601

申请日：2011-08-04

Applicant: Jeng-Jiun Yang ,  Constantin Bulucea

Inventor： Jeng-Jiun Yang ,  Constantin Bulucea

IPC: H01L27/06

CPC classification number: H01L27/0623 ,  H01L21/82285 ,  H01L21/8249 ,  H01L27/0826

Abstract: A semiconductor structure contains a bipolar transistor (101) and a spacing structure (265-1 or 265-2). The transistor has an emitter (241), a base (243), and a collector (245). The base is formed with an intrinsic base portion (243I), a base link portion (243L), and a base contact portion (245C). The intrinsic base portion is situated below the emitter and above material of the collector. The base link portion extends between the intrinsic base portion and the base contact portions. The spacing structure includes an isolating dielectric layer (267-1 or 267-2) and a spacing component. The dielectric layer extends along the upper semiconductor surface. The spacing component includes a lateral spacing portion (269-1 or 269-2) of largely non-monocrystalline semiconductor material, preferably polycrystalline semiconductor material, situated on the dielectric layer above the base link portion. Opposite first and second upper edges of the lateral spacing portion (275-1 and 277-1) laterally conform to opposite first and second lower edges (297-1 and 299-1) of the base link portion so as to determine, and thereby control, its length.

Abstract translation: 半导体结构包含双极晶体管（101）和间隔结构（265-1或265-2）。 晶体管具有发射极（241），基极（243）和集电极（245）。 基部形成有本征基部（243I），基部连接部（243L）和基部接触部（245C）。 本征基部位于发射极之下和集电极材料之上。 基部连接部在本征基部与基部接触部之间延伸。 间隔结构包括隔离电介质层（267-1或267-2）和间隔部件。 电介质层沿着上半导体表面延伸。 间隔部件包括位于基部连接部分上方的电介质层上的大部分非单晶半导体材料（优选多晶半导体材料）的侧向间隔部分（269-1或269-2）。 横向间隔部分（275-1和277-1）的相对的第一和第二上边缘横向地与基部连杆部分的相对的第一和第二下边缘（297-1和299-1）相一致，以便确定，从而 控制，其长度。

公开(公告)号：US20120181626A1

公开(公告)日：2012-07-19

申请号：US13298284

申请日：2011-11-16

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/1203

Abstract: An insulated-gate field-effect transistor (220U) is provided with an empty-well region for achieving high performance. The concentration of the body dopant reaches a maximum at a subsurface location no more than 10 times deeper below the upper semiconductor surface than the depth of one of a pair of source/drain zones (262 and 264), decreases by at least a factor of 10 in moving from the subsurface location along a selected vertical line (136U) through that source/drain zone to the upper semiconductor surface, and has a logarithm that decreases substantially monotonically and substantially inflectionlessly in moving from the subsurface location along the vertical line to that source/drain zone. Each source/drain zone has a main portion (262M or 264M) and a more lightly doped lateral extension (262E or 264E). Alternatively or additionally, a more heavily doped pocket portion (280) of the body material extends along one of the source/drain zones.

Abstract translation: 绝缘栅场效应晶体管（220U）具有用于实现高性能的空井区域。 身体掺杂物的浓度在上半导体表面下方比在一对源/漏区（262和264）之一的深度不超过10倍的地下位置处达到最大值，减小至少一个因子 10沿着沿着选择的垂直线（136U）通过该源极/漏极区域移动到上半导体表面的地下位置移动，并且具有从沿着垂直线的地下位置移动到基本单调和基本上无穷地基本上单调减小的对数， 源/漏区。 每个源/漏区具有主要部分（262M或264M）和更轻掺杂的横向延伸（262E或264E）。 替代地或另外地，主体材料的更重掺杂的凹穴部分（280）沿着源极/漏极区域中的一个延伸。