公开(公告)号：US20080191980A1

公开(公告)日：2008-08-14

申请号：US11929325

申请日：2007-10-30

Applicant: Sang-Jin Jeon

Inventor： Sang-Jin Jeon

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0223 ,  G11C19/184

Abstract: A display device includes driving apparatus having first, second, third, and fourth gate drivers. The first and second gate drivers are connected to gate lines and are positioned on one side of the display device side by side. The third and fourth gate drivers are connected to gate lines and are positioned on the other side of the display device side by side. The first and third gate drivers apply the gate signal to the same gate line, and the second and fourth gate drivers apply the gate signal to the same gate line.

Abstract translation: 显示装置包括具有第一，第二，第三和第四栅极驱动器的驱动装置。 第一和第二栅极驱动器连接到栅极线并且并排设置在显示装置的一侧。 第三和第四栅极驱动器连接到栅极线并且并排地定位在显示装置的另一侧上。 第一和第三栅极驱动器将栅极信号施加到同一个栅极线，第二和第四栅极驱动器将栅极信号施加到同一个栅极线。

公开(公告)号：US07271867B2

公开(公告)日：2007-09-18

申请号：US10273073

申请日：2002-10-17

Applicant: Jang-Soo Kim ,  Hyang-Shik Kong ,  Min-Wook Park ,  Sang-Jin Jeon

Inventor： Jang-Soo Kim ,  Hyang-Shik Kong ,  Min-Wook Park ,  Sang-Jin Jeon

IPC: G02F1/1333 ,  G02F1/136

CPC classification number: G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1288 ,  H01L29/66765

Abstract: A device and corresponding method of fabrication thereof are disclosed, where the device provides a contact for semiconductor and display devices, the device including a substrate, a first wiring line assembly formed on the substrate, an under-layer formed on the first wiring line assembly, an organic insulating layer formed on the under-layer such that the organic insulating layer covers the under-layer, a pattern on the organic insulating layer for contact holes to expose the under-layer, etched contact holes formed in the under-layer in correspondence with the pattern such that the underlying first wiring line assembly is exposed to the outside, a cured organic insulating layer formed on the under-layer, and a second wiring line assembly formed on the organic insulating layer such that the second wiring line assembly is connected to the first wiring line assembly through the etched contact holes; and the corresponding method of fabrication including forming a first wiring line assembly on a substrate, forming an under-layer on the first wiring line assembly, forming an organic insulating layer such that the organic insulating layer covers the under-layer, patterning the organic insulating layer to thereby form contact holes exposing the under-layer, etching the under-layer exposed through the contact holes such that the underlying first wiring line assembly is exposed to the outside, curing the organic insulating layer, and forming a second wiring line assembly on the organic insulating layer such that the second wiring line assembly is connected to the first wiring line assembly through the contact holes.

Abstract translation: 公开了一种器件及其相应的制造方法，其中器件为半导体和显示器件提供接触，该器件包括衬底，形成在衬底上的第一布线组件，形成在第一布线组件上的底层 形成在下层上的有机绝缘层，使得有机绝缘层覆盖下层，在有机绝缘层上形成用于接触孔的图案，以暴露下层中形成的下层的蚀刻接触孔， 与图案对应，使得下面的第一布线组件暴露于外部，形成在下层上的固化的有机绝缘层和形成在有机绝缘层上的第二布线组件，使得第二布线组件是 通过蚀刻的接触孔连接到第一布线组件; 以及相应的制造方法，包括在基板上形成第一布线线组件，在第一布线线路组件上形成底层，形成有机绝缘层，以使有机绝缘层覆盖下层，图案化有机绝缘层 从而形成暴露下层的接触孔，蚀刻通过接触孔暴露的下层，使得下面的第一布线线组件暴露于外部，固化有机绝缘层，并形成第二布线组件 所述有机绝缘层使得所述第二布线组合体通过所述接触孔连接到所述第一布线线组件。

公开(公告)号：US07119368B2

公开(公告)日：2006-10-10

申请号：US10926719

申请日：2004-08-26

Applicant: Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

Inventor： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

IPC: H01L31/0376

CPC classification number: G02F1/1368 ,  G02F1/1339

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

公开(公告)号：US07023016B2

公开(公告)日：2006-04-04

申请号：US10884083

申请日：2004-07-01

Applicant: Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

Inventor： Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

IPC: H01L29/04

CPC classification number: H01L27/12 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13629 ,  H01L27/124 ,  H01L27/1288

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

公开(公告)号：US20050110014A1

公开(公告)日：2005-05-26

申请号：US10922343

申请日：2004-08-19

Applicant: Min-Wook Park ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  Sang-Jin Jeon

Inventor： Min-Wook Park ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  Sang-Jin Jeon

IPC: G02F1/1339 ,  G02F1/136 ,  G02F1/1368 ,  G09F9/00 ,  G09F9/30 ,  H01L21/00 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L23/52 ,  H01L29/417 ,  H01L29/786 ,  H01L31/036

CPC classification number: H01L29/41733 ,  H01L27/124

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.