公开(公告)号：US06831503B2

公开(公告)日：2004-12-14

申请号：US10325609

申请日：2002-12-20

申请人： Francesco La Rosa

发明人： Francesco La Rosa

IPC分类号： G05F110

CPC分类号： G05F3/262

摘要： A current or voltage generator is integrated onto a silicon wafer and may include a first element including a first NMOS transistor having its source connected to ground through an electrical resistance, a second element including a second NMOS transistor having its source connected to ground, and a bias circuit for the first and second elements. The second element may include a voltage divider. The gate of the second NMOS transistor may be connected to a dividing node of the voltage divider, and the anode of the voltage divider may be connected to the gate of the first NMOS transistor. Both elements may be biased at an operating point corresponding to an identical temperature stability point for both elements.

摘要翻译： 电流或电压发生器被集成到硅晶片上，并且可以包括第一元件，其包括通过电阻将其源极连接到地的第一NMOS晶体管，包括其源极连接到地的第二NMOS晶体管的第二元件，以及 用于第一和第二元件的偏置电路。 第二元件可以包括分压器。 第二NMOS晶体管的栅极可以连接到分压器的分压节点，并且分压器的阳极可以连接到第一NMOS晶体管的栅极。 两个元件可能在对应于两个元件的相同温度稳定点的操作点处偏置。

公开(公告)号：US06760265B2

公开(公告)日：2004-07-06

申请号：US10299965

申请日：2002-11-19

申请人： Francesco La Rosa

发明人： Francesco La Rosa

IPC分类号： G11C700

CPC分类号： G11C7/062 ,  G11C16/28 ,  G11C2207/063

摘要： A read amplifier includes a read stage, a reference stage and a differential output stage that includes PMOS and NMOS transistors. The transistors of the differential stage include only one PMOS transistor and only one NMOS transistor in series. The PMOS transistor has its gate linked to one node of the read stage. The NMOS transistor has its gate linked to one node of the reference stage. The mid-point of the PMOS and NMOS transistors of the differential stage form a data output node of the read amplifier.

摘要翻译： 读放大器包括读阶段，参考级和包括PMOS和NMOS晶体管的差分输出级。 差分级的晶体管仅包括一个PMOS晶体管和仅一个NMOS晶体管串联。 PMOS晶体管的栅极连接到读取级的一个节点。 NMOS晶体管的栅极连接到参考级的一个节点。 差分级的PMOS和NMOS晶体管的中点形成读取放大器的数据输出节点。

公开(公告)号：US06738286B2

公开(公告)日：2004-05-18

申请号：US10277183

申请日：2002-10-21

申请人： Francesco La Rosa

发明人： Francesco La Rosa

IPC分类号： G11C1604

CPC分类号： G11C16/20

摘要： An electrically erasable and programmable memory (EEPROM) includes a memory array containing memory cells connected to word lines arranged in rows and to bit lines arranged in columns. The memory array includes a first special zone for storing special bits of a first type, and a second special zone for storing special bits of a second type. The first special zone includes a first row of memory cells connected to a first word line, wherein N1 memory cells are connected to N1 bit lines of a determined column of the memory array. The second special zone includes a second row of memory cells connected to a second word line, wherein N2 memory cells are connected to N2 other bit lines of the determined column. The N1 bit lines are not connected to the second row of memory cells, and the N2 bit lines are not connected to the first row of memory cells.

摘要翻译： 电可擦除可编程存储器（EEPROM）包括存储器阵列，存储器阵列包含连接到排列成行的字线和以列排列的位线的存储器单元。 存储器阵列包括用于存储第一类型的特殊位的第一特殊区域和用于存储第二类型的特殊位的第二特殊区域。 第一特殊区域包括连接到第一字线的第一行存储器单元，其中N1个存储器单元连接到存储器阵列的确定列的N1位线。 第二特殊区域包括连接到第二字线的第二行存储单元，其中N2个存储单元连接到所确定列的N2个其它位线。 N1位线未连接到第二行存储单元，N2位线未连接到第一行存储单元。

公开(公告)号：US06724243B2

公开(公告)日：2004-04-20

申请号：US10164840

申请日：2002-06-06

申请人： Francesco La Rosa

发明人： Francesco La Rosa

IPC分类号： G05F110

CPC分类号： G05F3/205 ,  G05F3/262

摘要： A bias circuit integrated on a silicon wafer includes first, second and third branches. The first branch includes a first PMOS transistor in series with a first NMOS transistor. The second branch includes a second PMOS transistor, a second NMOS transistor and an electric resistor in series. The gate of the first NMOS transistor is connected to the gate of the second NMOS transistor. The first branch and the second branch are arranged as a current mirror. The third branch includes a third PMOS transistor in series with a third NMOS transistor. The third PMOS and NMOS transistors are arranged to maintain a drain voltage of the first PMOS transistor that is substantially identical to a drain voltage of the second PMOS transistor.

摘要翻译： 集成在硅晶片上的偏置电路包括第一，第二和第三分支。 第一分支包括与第一NMOS晶体管串联的第一PMOS晶体管。 第二分支包括第二PMOS晶体管，第二NMOS晶体管和串联的电阻器。 第一NMOS晶体管的栅极连接到第二NMOS晶体管的栅极。 第一分支和第二分支被布置为电流镜。 第三分支包括与第三NMOS晶体管串联的第三PMOS晶体管。 第三PMOS和NMOS晶体管布置成保持第一PMOS晶体管的漏极电压基本上等于第二PMOS晶体管的漏极电压。

公开(公告)号：US06563344B2

公开(公告)日：2003-05-13

申请号：US09935292

申请日：2001-08-22

申请人： Francesco La Rosa

发明人： Francesco La Rosa

IPC分类号： H03K1900

CPC分类号： G11C7/225 ,  G11C7/22 ,  H03K19/00361

摘要： A buffer circuit includes an input for receiving a logic signal, and a transfer circuit for transferring the logic signal from the input to an output of the buffer circuit. The transfer circuit includes at least one logic gate having a trip point sensitive to a supply voltage of the buffer circuit. The buffer circuit further includes a delivery circuit for delivering an inhibit signal having a predetermined duration when the logic signal has a trailing edge and/or leading edge, and an inhibit circuit for inhibiting the transfer circuit and for isolating the output of the buffer circuit from the input of the buffer circuit when the inhibit signal is delivered. A storage circuit holds a logic value of the logic signal at the output of the buffer circuit when the inhibit signal is delivered.

公开(公告)号：US08872177B2

公开(公告)日：2014-10-28

申请号：US13615309

申请日：2012-09-13

申请人： Francesco La Rosa ,  Pascal Fornara

发明人： Francesco La Rosa ,  Pascal Fornara

IPC分类号： H01L23/58 ,  H01L29/94 ,  H01L49/02 ,  H01L21/84 ,  H01L23/522 ,  G04F13/00 ,  G11C27/02 ,  H01L27/08 ,  H01L27/12

CPC分类号： G01R27/2605 ,  G01R17/02 ,  G04F10/10 ,  G04F13/00 ,  G11C11/24 ,  G11C27/024 ,  H01G4/005 ,  H01G4/018 ,  H01G4/38 ,  H01L21/84 ,  H01L23/5223 ,  H01L27/0805 ,  H01L27/1203 ,  H01L28/40 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： A charge flow circuit for a time measurement, including a plurality of elementary capacitive elements electrically in series, each elementary capacitive element leaking through its dielectric space.

摘要翻译： 一种用于时间测量的电荷流动电路，包括电串联的多个基本电容元件，每个元件电容元件通过其介电空间泄漏。

公开(公告)号：US08391079B2

公开(公告)日：2013-03-05

申请号：US12823901

申请日：2010-06-25

申请人： Francesco La Rosa

发明人： Francesco La Rosa

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0433 ,  G11C8/12 ,  G11C16/16 ,  G11C2216/04

摘要： The present disclosure relates to an electrically erasable and programmable memory comprising rows of memory cells to store words of N bits each, bit lines and word lines, wherein a row of memory cells comprises a first group of memory cells to store collectively erasable words, and at least one second group of memory cells to store one individually erasable word.

摘要翻译： 本发明涉及一种电可擦除和可编程存储器，其包括存储单元行，每行存储N位的字，位线和字线，其中一行存储器单元包括第一组存储器单元以存储集体可擦除字，以及 至少一个第二组存储器单元，用于存储一个单独的可擦除字。

公开(公告)号：US08363499B2

公开(公告)日：2013-01-29

申请号：US12844472

申请日：2010-07-27

申请人： Francesco La Rosa

发明人： Francesco La Rosa

IPC分类号： G11C7/06

CPC分类号： G11C16/28 ,  G11C7/065 ,  G11C7/08

摘要： A sense amplifier is disclosed comprising a first sense input, a second sense input, a latch, a first p-channel control transistor arranged to electrically power a first section of the latch and having a gate terminal linked to the first sense input, and a second p-channel control transistor arranged to electrically power a second section of the latch and having a gate terminal linked to the second sense input. Application may be in particular to low power embedded memories.

摘要翻译： 公开了一种读出放大器，包括第一感测输入，第二感测输入，锁存器，第一p沟道控制晶体管，被配置为对锁存器的第一部分供电并且具有链接到第一感测输入端的栅极端子，以及 第二p沟道控制晶体管，其布置成对所述锁存器的第二部分供电并且具有链接到所述第二检测输入的栅极端子。 应用可能特别是低功率嵌入式存储器。

公开(公告)号：US08050107B2

公开(公告)日：2011-11-01

申请号：US12113721

申请日：2008-05-01

申请人： Francesco La Rosa ,  Antonino Conte

发明人： Francesco La Rosa ,  Antonino Conte

IPC分类号： G11C16/04

CPC分类号： G11C16/225 ,  G11C16/102

摘要： A method writes data in a non-volatile memory. The method provides, in the memory, a non-volatile main memory area comprising target pages, a non-volatile auxiliary memory area comprising auxiliary pages, and, in the auxiliary memory area: a current sector comprising erased auxiliary pages usable to write data, a save sector comprising auxiliary pages comprising data linked to target pages to be erased or being erased, a transfer sector comprising auxiliary pages including data to be transferred to erased target pages, and an unavailable sector comprising auxiliary pages to be erased or being erased. The method can be applied in particular to FLASH memories.

摘要翻译： 一种方法将数据写入非易失性存储器。 该方法在存储器中提供包括目标页面的非易失性主存储器区域，包括辅助页面的非易失性辅助存储器区域，并且在辅助存储器区域中：包括可用于写入数据的擦除辅助页面的当前扇区， 包括辅助页面的保存扇区，包括链接到要擦除或被擦除的目标页面的数据，包括辅助页面的传送扇区，包括要传送到已擦除的目标页面的数据，以及包括要被擦除或被擦除的辅助页面的不可用扇区。 该方法可以特别地应用于闪速存储器。

公开(公告)号：US20110215862A1

公开(公告)日：2011-09-08

申请号：US13038160

申请日：2011-03-01

申请人： Francesco La Rosa

发明人： Francesco La Rosa

IPC分类号： G05F1/10 ,  G05F3/16

CPC分类号： G05F3/24 ,  H03K19/00384 ,  H03K2005/00136

摘要： The disclosure relates to a method for generating a setpoint voltage in an integrated circuit, comprising generating a substantially constant reference voltage, and generating from the reference voltage, a setpoint voltage comprising a component equal to the highest threshold voltage of all the CMOS transistors of a circuit of the integrated circuit and a component which may be equal to zero. The disclosure applies in particular to the provision of a power supply voltage of a circuit based on CMOS transistors.

摘要翻译： 本公开涉及一种用于在集成电路中产生设定点电压的方法，包括生成基本恒定的参考电压，并从参考电压产生包括等于所有CMOS晶体管的最高阈值电压的分量的设定点电压 集成电路的电路和可等于零的分量。 本公开特别涉及提供基于CMOS晶体管的电路的电源电压。