公开(公告)号：US08835923B2

公开(公告)日：2014-09-16

申请号：US13616603

申请日：2012-09-14

申请人： Pascal Fornara

发明人： Pascal Fornara

IPC分类号： H01L29/10 ,  H01L21/66 ,  H01L21/30 ,  H01L21/31 ,  H01L23/58

CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor wafer for a silicon-on-insulator integrated circuit comprises an insulating region located between a first semiconductor substrate intended to receive the integrated circuit and a second semiconductor substrate containing at least one buried layer comprising at least one metal silicide.

摘要翻译： 用于绝缘体上硅集成电路的半导体晶片包括位于用于接收集成电路的第一半导体衬底和含有至少一个包含至少一种金属硅化物的掩埋层的第二半导体衬底之间的绝缘区域。

公开(公告)号：US20140209141A1

公开(公告)日：2014-07-31

申请号：US14232606

申请日：2012-07-05

申请人： Pascal Fornara ,  Christian Rivero

发明人： Pascal Fornara ,  Christian Rivero

IPC分类号： H01L27/16 ,  H01L35/32

CPC分类号： H01L27/16 ,  H01L35/32 ,  H01L35/325 ,  H01L2224/16225 ,  H01L2924/15311

摘要： Method for generation of electrical power within a three-dimensional integrated structure comprising several elements electrically interconnected by a link device, the method comprising the production of a temperature gradient in at least one region of the link device resulting from the operation of at least one of the said elements, and the production of electrical power using at least one thermo-electric generator comprising at least one assembly of thermocouples electrically connected in series and thermally connected in parallel and contained within the said region subjected to the said temperature gradient.

摘要翻译： 一种在三维一体化结构内产生电功率的方法，包括通过连接装置电互连的多个元件，所述方法包括在连接装置的至少一个区域中产生温度梯度，所述至少一个区域是由 所述元件和使用至少一个热电发生器的电力的产生，所述至少一个热电发生器包括串联电连接并并联并热并连接并且包含在经受所述温度梯度的所述区域内的热电偶的至少一个组件。

公开(公告)号：US20140070829A1

公开(公告)日：2014-03-13

申请号：US14082818

申请日：2013-11-18

申请人： Pascal Fornara ,  Christian Rivero

发明人： Pascal Fornara ,  Christian Rivero

IPC分类号： G01R31/28

CPC分类号： G01R31/2851 ,  G01L9/0042 ,  G06K19/07363 ,  G06K19/07381 ,  H01L22/34 ,  H01L23/576 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device for detecting the thinning down of the substrate of an integrated circuit chip, including, in the active area of the substrate, bar-shaped diffused resistors connected as a Wheatstone bridge, wherein: first opposite resistors of the bridge are oriented along a first direction; the second opposite resistors of the bridge are oriented along a second direction; and the first and second directions are such that a thinning down of the substrate causes a variation of the imbalance value of the bridge.

摘要翻译： 一种用于检测集成电路芯片的基板的减薄的装置，包括在基板的有源区域中连接为惠斯通电桥的条形扩散电阻器，其中：桥的第一相对电阻器沿第一 方向; 桥的第二相对电阻器沿着第二方向定向; 并且第一和第二方向使得衬底的变薄导致桥的不平衡值的变化。

公开(公告)号：US08618821B2

公开(公告)日：2013-12-31

申请号：US12797897

申请日：2010-06-10

申请人： Pascal Fornara ,  Christian Rivero

发明人： Pascal Fornara ,  Christian Rivero

IPC分类号： G01R27/08

CPC分类号： G01R31/2851 ,  G01L9/0042 ,  G06K19/07363 ,  G06K19/07381 ,  H01L22/34 ,  H01L23/576 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device for detecting the thinning down of the substrate of an integrated circuit chip, including, in the active area of the substrate, bar-shaped diffused resistors connected as a Wheatstone bridge, wherein: first opposite resistors of the bridge are oriented along a first direction; the second opposite resistors of the bridge are oriented along a second direction; and the first and second directions are such that a thinning down of the substrate causes a variation of the imbalance value of the bridge.

公开(公告)号：US08532947B2

公开(公告)日：2013-09-10

申请号：US12969266

申请日：2010-12-15

申请人： Pascal Fornara ,  Mathieu Lisart

发明人： Pascal Fornara ,  Mathieu Lisart

IPC分类号： G01R19/00 ,  G06F19/00

CPC分类号： G06K19/067 ,  H01L23/48 ,  H01L23/544 ,  H01L2223/54433 ,  H01L2223/54446 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes non-volatile storage configured to secretly store a digital word, the value of which forms an identification code. The integrated circuit also includes control circuitry configured to receive the digital word and to generate transient electrical currents or transient voltages, the characteristics of which depend on the value of the digital word. There is an electrically conductive network configured to be passed through by the electrical currents or receive the transient voltages so as to generate an electromagnetic field that identifies the integrated circuit.

摘要翻译： 集成电路包括被配置为秘密地存储数字字的非易失性存储器，其数值字形成识别码。 集成电路还包括配置成接收数字字并产生瞬态电流或瞬态电压的控制电路，其特性取决于数字字的值。 存在导电网络，其配置为通过电流通过或接收瞬态电压，以便产生识别集成电路的电磁场。

公开(公告)号：US20130075726A1

公开(公告)日：2013-03-28

申请号：US13616603

申请日：2012-09-14

申请人： Pascal Fornara

发明人： Pascal Fornara

IPC分类号： H01L23/544 ,  H01L21/762 ,  H01L21/66 ,  H01L21/28

CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor wafer for a silicon-on-insulator integrated circuit comprises an insulating region located between a first semiconductor substrate intended to receive the integrated circuit and a second semiconductor substrate containing at least one buried layer comprising at least one metal silicide.

摘要翻译： 用于绝缘体上硅集成电路的半导体晶片包括位于用于接收集成电路的第一半导体衬底和含有至少一个包含至少一种金属硅化物的掩埋层的第二半导体衬底之间的绝缘区域。

公开(公告)号：US20130032926A1

公开(公告)日：2013-02-07

申请号：US13552973

申请日：2012-07-19

申请人： Pascal FORNARA ,  Arnaud Regnier

发明人： Pascal FORNARA ,  Arnaud Regnier

IPC分类号： H01L27/08

CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11531

摘要： An adjustable resistor formed on a first insulating layer of a substrate, including: a first polysilicon layer covered with a second insulating layer of a first thickness, except in a region where the first polysilicon layer is covered with a thin insulator layer of a second thickness smaller than the first thickness; a second polysilicon layer covering the second insulating layer and the thin insulator layer; on each side of the second insulating layer and at a distance from it, a first and a second conductive vias providing access to the terminals of the resistor on the first polysilicon layer; and a third conductive via providing access to a contacting area on the second polysilicon layer.

摘要翻译： 一种形成在基板的第一绝缘层上的可调电阻器，包括：第一多晶硅层，其被第一厚度的第二绝缘层覆盖，除了第一多晶硅层被第二厚度的薄绝缘层覆盖的区域之外 小于第一厚度; 覆盖所述第二绝缘层和所述薄绝缘体层的第二多晶硅层; 在所述第二绝缘层的每一侧上与所述第二绝缘层相距一定距离处的第一和第二导电通孔提供对所述第一多晶硅层上的所述电阻器的端子的访问; 以及第三导电通孔，其提供对所述第二多晶硅层上的接触区域的接近。

公开(公告)号：US08344391B2

公开(公告)日：2013-01-01

申请号：US12538336

申请日：2009-08-10

申请人： Pascal Fornara ,  Fabrice Marinet

发明人： Pascal Fornara ,  Fabrice Marinet

IPC分类号： H01L27/15 ,  H01L29/26 ,  H01L31/12 ,  H01L33/00

CPC分类号： H01L27/101 ,  G11C17/16 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521

摘要： An integrated circuit including a substrate of a semiconductor material and first metal portions of a first metallization level or of a first via level defining pixels of an image. The pixels are distributed in first pixels, for each of which the first metal portion is connected to the substrate, and in second pixels, for each of which the first metal portion is separated from the substrate by at least one insulating portion.

摘要翻译： 一种集成电路，包括半导体材料的衬底和第一金属化级的第一金属部分或限定图像像素的第一通孔级。 像素分布在第一像素中，其中第一金属部分连接到基板，并且在第二像素中，其中第一金属部分通过至少一个绝缘部分与基板分离。

公开(公告)号：US08779552B2

公开(公告)日：2014-07-15

申请号：US12897231

申请日：2010-10-04

申请人： Pascal Fornara ,  Fabrice Marinet

发明人： Pascal Fornara ,  Fabrice Marinet

IPC分类号： H01L29/72

CPC分类号： H01L23/573 ,  H01L21/26506 ,  H01L21/3221 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit chip formed inside and on top of a semiconductor substrate and including: in the upper portion of the substrate, an active portion in which components are formed; and under the active portion and at a depth ranging between 5 and 50 μm from the upper surface of the substrate, an area comprising sites for gettering metal impurities and containing metal atoms at a concentration ranging between 1017 and 1018 atoms/cm3.

摘要翻译： 一种集成电路芯片，形成在半导体衬底的内部和顶部，并且包括：在衬底的上部，形成有部件的有源部分; 并且在活性部分和距离衬底的上表面5至50μm之间的深度范围内，包括用于吸收金属杂质并且含有浓度范围为1017至1018原子/ cm3之间的金属原子的位置的区域。

公开(公告)号：US08729668B2

公开(公告)日：2014-05-20

申请号：US13552973

申请日：2012-07-19

申请人： Pascal Fornara ,  Arnaud Regnier

发明人： Pascal Fornara ,  Arnaud Regnier

IPC分类号： H01L21/02

CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11531

摘要： An adjustable resistor formed on a first insulating layer of a substrate, including: a first polysilicon layer covered with a second insulating layer of a first thickness, except in a region where the first polysilicon layer is covered with a thin insulator layer of a second thickness smaller than the first thickness; a second polysilicon layer covering the second insulating layer and the thin insulator layer; on each side of the second insulating layer and at a distance from it, a first and a second conductive vias providing access to the terminals of the resistor on the first polysilicon layer; and a third conductive via providing access to a contacting area on the second polysilicon layer.

摘要翻译： 一种形成在基板的第一绝缘层上的可调电阻器，包括：第一多晶硅层，其被第一厚度的第二绝缘层覆盖，除了第一多晶硅层被第二厚度的薄绝缘层覆盖的区域之外 小于第一厚度; 覆盖所述第二绝缘层和所述薄绝缘体层的第二多晶硅层; 在所述第二绝缘层的每一侧上与所述第二绝缘层相距一定距离处的第一和第二导电通孔提供对所述第一多晶硅层上的所述电阻器的端子的访问; 以及第三导电通孔，其提供对所述第二多晶硅层上的接触区域的接近。