公开(公告)号：US06830978B2

公开(公告)日：2004-12-14

申请号：US10643970

申请日：2003-08-20

Applicant: Junichi Ariyoshi ,  Satoshi Torii

Inventor： Junichi Ariyoshi ,  Satoshi Torii

IPC: H01I21336

CPC classification number: H01L27/11526 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/11546 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

Abstract: On a semiconductor substrate having a gate electrode and an LDD layer formed thereon, an SiN film to be a silicide block is formed. An opening communicating with the LDD layer is provided for the SiN film. Impurities are introduced into the LDD layer through the opening to form a source/drain layer, and the surface thereof is silicided to form a silicide film. Next, an interlayer insulation film of SiO2 is formed and then etched under a condition of an etching rate of SiO2 higher than that of SiN to form a contact hole reaching the LDD layer from the upper surface of the interlayer insulation film via the opening.

Abstract translation: 在其上形成有栅电极和LDD层的半导体衬底上，形成作为硅化物块的SiN膜。 为SiN膜提供与LDD层连通的开口。 通过开口将杂质引入LDD层以形成源/漏层，并将其表面硅化以形成硅化物膜。 接下来，形成SiO 2的层间绝缘膜，然后在SiO x的蚀刻速率高于SiN的蚀刻速率的条件下进行蚀刻，以形成从层间绝缘膜的上表面经由开口到达LDD层的接触孔。

公开(公告)号：US06735127B2

公开(公告)日：2004-05-11

申请号：US10160050

申请日：2002-06-04

Applicant: Satoshi Torii

Inventor： Satoshi Torii

IPC: G11C1604

CPC classification number: H01L27/11568 ,  G11C16/0466 ,  G11C16/0491 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/115 ,  H01L29/792

Abstract: A method of driving a semiconductor memory having a semiconductor substrate, spaced apart first and second impurity diffusion regions disposed in partial surface layers of the substrate, a gate electrode, and a gate insulating film between a channel region and the gate electrode. A portion is disposed in a partial area along the longitudinal direction of a path interconnecting the diffusion regions, and a charge trap film and a second insulating film are sequentially stacked, the charge trap film being made of insulating material easier to trap electrons than the first and second insulating films. The method has a hole drain step of draining holes trapped in each film between the gate electrode and the channel region or at an interface between adjacent films, by applying a hole drain voltage to the gate electrode, higher than a voltage applied to either the first or second impurity diffusion region.

Abstract translation: 一种驱动半导体存储器的方法，所述半导体存储器具有设置在所述衬底的部分表面层中的间隔开的第一和第二杂质扩散区域，栅电极和栅极绝缘膜之间的半导体衬底。 一部分沿着连接扩散区域的路径的纵向方向设置在部分区域中，并且电荷陷阱膜和第二绝缘膜依次层叠，电荷陷阱膜由绝缘材料制成，比第一 和第二绝缘膜。 该方法具有漏极步骤，通过向栅电极施加漏极电压，高于施加到第一栅极电极和沟道区域之间的电压，在栅极电极和沟道区域之间或在相邻膜之间的界面处捕集每个膜中的空穴 或第二杂质扩散区。

公开(公告)号：US09287277B2

公开(公告)日：2016-03-15

申请号：US13542759

申请日：2012-07-06

Applicant: Tatsuya Sugimachi ,  Satoshi Torii

Inventor： Tatsuya Sugimachi ,  Satoshi Torii

IPC: H01L29/788 ,  H01L27/115 ,  H01L21/8234 ,  G11C16/04 ,  H01L29/66

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  H01L21/823468 ,  H01L27/11524 ,  H01L29/6656

Abstract: A semiconductor device includes: a memory cell transistor which has a floating gate, a control gate, and a source and a drain formed in a semiconductor substrate on both sides of the floating gate via a channel area; and a selecting transistor which has a select gate and a source and a drain formed in the semiconductor substrate on both sides of the select gate, wherein the source of the selecting transistor is connected to the drain of the memory cell transistor, the source of the memory cell transistor has an N-type first impurity diffusion layer, an N-type second impurity diffusion layer deeper than the first impurity diffusion layer, and an N-type third impurity diffusion layer which is shallower than the second impurity diffusion layer, and an impurity density of the second impurity diffusion layer is lower than that of the third impurity diffusion layer.

公开(公告)号：US08897079B2

公开(公告)日：2014-11-25

申请号：US13426463

申请日：2012-03-21

Applicant: Satoshi Torii

Inventor： Satoshi Torii

IPC: G11C16/06 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/06 ,  G11C16/0416 ,  G11C16/0483 ,  G11C16/349

Abstract: Local bit lines (LBL) are respectively provided for a plurality of sectors, corresponding to each of the global bit lines (GBL). Sector select transistors connect a LBL to a GBLector select lines control the on/off state of the sector select transistors for the corresponding sectors. A plurality of word lines (WL) intersect the local bit lines. Memory cells are located at the intersections between the LBL and the WL. Each memory cell connects a source line with the corresponding LBL and includes an n-channel transistor that is turned on/off by the corresponding WL. A precharge voltage is applied to a charging line. Charging transistors connect the LBL to the charging line. A charging gate line controls the on/off state of the charging transistors.

Abstract translation: 对于与全局位线（GBL）中的每一个相对应的多个扇区，分别提供局部位线（LBL）。 扇区选择晶体管将LBL连接到GBLector选择线控制相应扇区的扇区选择晶体管的开/关状态。 多个字线（WL）与局部位线相交。 存储单元位于LBL和WL之间的交点处。 每个存储单元将源极线与相应的LBL连接，并且包括由对应的WL导通/截止的n沟道晶体管。 预充电电压施加到充电线。 充电晶体管将LBL连接到充电线。 充电栅极线控制充电晶体管的导通/截止状态。

公开(公告)号：US08604533B2

公开(公告)日：2013-12-10

申请号：US12537913

申请日：2009-08-07

Applicant: Tatsuya Sugimachi ,  Satoshi Torii

Inventor： Tatsuya Sugimachi ,  Satoshi Torii

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  H01L21/823468 ,  H01L27/11524 ,  H01L29/6656

Abstract: A semiconductor device includes: a memory cell transistor which has a floating gate, a control gate, and a source and a drain formed in a semiconductor substrate on both sides of the floating gate via a channel area; and a selecting transistor which has a select gate and a source and a drain formed in the semiconductor substrate on both sides of the select gate, wherein the source of the selecting transistor is connected to the drain of the memory cell transistor, the source of the memory cell transistor has an N-type first impurity diffusion layer, an N-type second impurity diffusion layer deeper than the first impurity diffusion layer, and an N-type third impurity diffusion layer which is shallower than the second impurity diffusion layer, and an impurity density of the second impurity diffusion layer is lower than that of the third impurity diffusion layer.

Abstract translation: 半导体器件包括：存储单元晶体管，其具有浮置栅极，控制栅极，以及经由沟道区域形成在浮置栅极两侧的半导体衬底中的源极和漏极; 以及选择晶体管，其具有在所述选择栅极的两侧上形成在所述半导体衬底中的选择栅极和源极和漏极，其中所述选择晶体管的源极连接到所述存储单元晶体管的漏极， 存储单元晶体管具有N型第一杂质扩散层，比第一杂质扩散层更深的N型第二杂质扩散层和比第二杂质扩散层浅的N型第三杂质扩散层， 第二杂质扩散层的杂质浓度低于第三杂质扩散层的杂质浓度。

公开(公告)号：US08233321B2

公开(公告)日：2012-07-31

申请号：US13197264

申请日：2011-08-03

Applicant: Satoshi Torii

Inventor： Satoshi Torii

IPC: G11C11/34 ,  G11C16/04 ,  G11C5/06

CPC classification number: H01L27/11519 ,  G11C16/0416 ,  G11C16/10 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11573

Abstract: A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control gates of the plural memory cell transistors present in a identical first direction; a plurality of source lines commonly coupling the sources of the plural memory cell transistors present in the identical first direction; a plurality of bit lines commonly coupling the drains of the plural memory cell transistors present in a identical second direction intersecting the first direction; a first transistor having a drain coupled to the source line; a second transistor having a drain coupled to a source of the first transistor, a gate coupled to the word line and a source grounded; and a control line commonly coupling the gates of the plural first transistors.

公开(公告)号：US08119477B2

公开(公告)日：2012-02-21

申请号：US11469164

申请日：2006-08-31

Applicant: Hidehiko Shiraiwa ,  YouSeok Suh ,  Harpreet Sachar ,  Satoshi Torii

Inventor： Hidehiko Shiraiwa ,  YouSeok Suh ,  Harpreet Sachar ,  Satoshi Torii

IPC: H01L21/331

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568

Abstract: A memory system is provided including forming a memory gate stack having a charge trap layer over a semiconductor substrate, forming a protection layer to cover the memory gate stack, and forming a protection enclosure for the charge trap layer with the protection layer and the memory gate stack.

Abstract translation: 提供了一种存储器系统，包括形成在半导体衬底上具有电荷陷阱层的存储器栅极堆叠，形成覆盖存储器栅极堆叠的保护层，以及形成用于具有保护层和存储栅极的电荷陷阱层的保护外壳 堆栈

公开(公告)号：US20110286277A1

公开(公告)日：2011-11-24

申请号：US13197280

申请日：2011-08-03

Applicant: Satoshi Torii

Inventor： Satoshi Torii

IPC: G11C16/26

CPC classification number: H01L27/11519 ,  G11C16/0416 ,  G11C16/10 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11573

Abstract: A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control gates of the plural memory cell transistors present in a identical first direction; a plurality of source lines commonly coupling the sources of the plural memory cell transistors present in the identical first direction; a plurality of bit lines commonly coupling the drains of the plural memory cell transistors present in a identical second direction intersecting the first direction; a first transistor having a drain coupled to the source line; a second transistor having a drain coupled to a source of the first transistor, a gate coupled to the word line and a source grounded; and a control line commonly coupling the gates of the plural first transistors.

公开(公告)号：US08014198B2

公开(公告)日：2011-09-06

申请号：US12411938

申请日：2009-03-26

Applicant: Satoshi Torii ,  Kazuhiro Mizutani ,  Toshio Nomura ,  Masayoshi Asano ,  Ikuto Fukuoka ,  Hiroshi Mawatari ,  Motoi Takahashi

Inventor： Satoshi Torii ,  Kazuhiro Mizutani ,  Toshio Nomura ,  Masayoshi Asano ,  Ikuto Fukuoka ,  Hiroshi Mawatari ,  Motoi Takahashi

IPC: G11C16/04 ,  G11C29/792 ,  G11C16/06

CPC classification number: G11C16/0433 ,  G11C16/10 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

Abstract translation: 一种非易失性半导体存储器件，包括以矩阵形式布置的存储单元阵列，每个存储单元阵列包括选择晶体管和存储单元晶体管; 控制位线电位的列解码器; 电压施加电路，控制第一字线的电位; 控制第二字线的电位的第一行解码器; 以及控制源极线的电位的第二行解码器。 列解码器由耐压低于电压施加电路和第二行解码器的电路形成。

公开(公告)号：US20110044112A1

公开(公告)日：2011-02-24

申请号：US12892388

申请日：2010-09-28

Applicant: Satoshi Torii

Inventor： Satoshi Torii

IPC: G11C16/04 ,  H01L29/792 ,  H01L29/788

CPC classification number: H01L27/11568 ,  G11C16/0433 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11565 ,  H01L29/7881

Abstract: A semiconductor device includes a first memory cell which includes a first memory transistor and a first selector transistor. The semiconductor device further includes a second memory cell which includes a second memory transistor and a second selector transistor. The semiconductor device further includes a first word line electrically coupled to a gate electrode of the first memory transistor and to a gate electrode of the second selector transistor, and a second word line electrically coupled to a gate electrode of the second memory transistor and to a gate electrode of the first selector transistor. The semiconductor device further includes a first source line electrically coupled to a source region of the first memory transistor and to a source region of the second memory transistor.

Abstract translation: 半导体器件包括第一存储单元，其包括第一存储晶体管和第一选择晶体管。 半导体器件还包括第二存储单元，其包括第二存储晶体管和第二选择晶体管。 半导体器件还包括电耦合到第一存储晶体管的栅电极和第二选择晶体管的栅电极的第一字线，以及电耦合到第二存储晶体管的栅电极的第二字线， 第一选择晶体管的栅电极。 半导体器件还包括电耦合到第一存储晶体管的源极区域和第二存储晶体管的源极区域的第一源极线。