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175 条记录 (耗时 0.038 秒)

    Methods and systems for sorting unaddressed items
    41.
    发明授权
    Methods and systems for sorting unaddressed items 有权
    排除未编址项目的方法和系统

    公开(公告)号：US08078313B2

    公开(公告)日：2011-12-13

    申请号：US10952818

    申请日：2004-09-30

    申请人： Glenn Edward McDonald ,  Wilson Wong

    发明人： Glenn Edward McDonald ,  Wilson Wong

    IPC分类号： G06F7/00

    CPC分类号： B07C3/00 ,  Y10S209/90

    摘要： Systems and methods for sorting a plurality of unaddressed items may comprise receiving delivery point address data. Furthermore, systems and methods for sorting a plurality of unaddressed items may comprise sorting the plurality of unaddressed items based on the delivery point address data. The plurality of unaddressed items may be sorted in an order in which they are to be delivered within a delivery zone specified by the delivery point address data.

    摘要翻译： 用于排序多个未寻址的物品的系统和方法可以包括接收递送点地址数据。 此外，用于排序多个未寻址项目的系统和方法可以包括基于递送点地址数据对多个未寻址项目进行排序。 多个未解决的项目可以按照它们在由递送点地址数据指定的递送区域内被递送的顺序进行排序。

    SIGNAL LOSS DETECTOR FOR HIGH-SPEED SERIAL INTERFACE OF A PROGRAMMABLE LOGIC DEVICE
    42.
    发明申请
    SIGNAL LOSS DETECTOR FOR HIGH-SPEED SERIAL INTERFACE OF A PROGRAMMABLE LOGIC DEVICE 有权
    用于可编程逻辑器件高速串行接口的信号丢失检测器

    公开(公告)号：US20110235756A1

    公开(公告)日：2011-09-29

    申请号：US13151717

    申请日：2011-06-02

    申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

    发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

    IPC分类号： H04L27/06

    CPC分类号： H04L25/45

    摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.

    摘要翻译： 信号丢失检测器包括对输入数据进行数字和模拟监测。 输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。 如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

    Power supply filtering for programmable logic device having heterogeneous serial interface architecture
    43.
    发明授权
    Power supply filtering for programmable logic device having heterogeneous serial interface architecture 有权
    具有异构串行接口架构的可编程逻辑器件的电源滤波

    公开(公告)号：US07903679B1

    公开(公告)日：2011-03-08

    申请号：US11622396

    申请日：2007-01-11

    申请人： Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

    发明人： Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

    IPC分类号： H04L12/56

    CPC分类号： H03K19/17744

    摘要： In a programmable logic device with a number of different types of serial interfaces, different power supply filtering schemes are applied to different interfaces. For interfaces operating at the lowest data rates—e.g., 1 Gbps—circuit-board level filtering including one or more decoupling capacitors may be provided. For interfaces operating at somewhat higher data rates—e.g., 3 Gbps—modest on-package filtering also may be provided, which may include power-island decoupling. For interfaces operating at still higher data rates—e.g., 6 Gbps—more substantial on-package filtering, including one or more on-package decoupling capacitors, also may be provided. For interfaces operating at the highest data rates—e.g., 10 Gbps—on-die filtering, which may include one or more on-die filtering or regulating networks, may be provided. The on-die regulators may be programmably bypassable allowing a user to trade off performance for power savings.

    摘要翻译： 在具有多种不同类型的串行接口的可编程逻辑器件中，不同的电源滤波方案被应用于不同的接口。 对于以最低数据速率操作的接口，例如，可以提供包括一个或多个去耦电容器的1Gbps电路板电平滤波器。 对于以较高数据速率工作的接口，例如，也可以提供3 Gbps适度的封装内滤波，这可能包括功率岛解耦。 对于以更高的数据速率运行的接口，例如，也可以提供包括一个或多个封装内去耦电容器的6Gbps更实质的封装内滤波。 对于以最高数据速率工作的接口，例如，可以提供10Gbps片上滤波，其可以包括一个或多个片上滤波或调节网络。 片上调节器可以可编程地旁路，允许用户权衡功能以节省功率。

    Techniques for Boundary Scan Testing Using Transmitters and Receivers
    45.
    发明申请
    Techniques for Boundary Scan Testing Using Transmitters and Receivers 有权
    使用发射机和接收机进行边界扫描测试的技术

    公开(公告)号：US20100262877A1

    公开(公告)日：2010-10-14

    申请号：US12422916

    申请日：2009-04-13

    申请人： Sriram Narayan ,  Xiaoyan Su ,  Wilson Wong

    发明人： Sriram Narayan ,  Xiaoyan Su ,  Wilson Wong

    IPC分类号： G01R31/3177 ,  G06F11/25

    CPC分类号： G01R31/318572

    摘要： A test driver transmitter drives a test signal through a resistive termination circuit to a first pin to test components on a board during a boundary scan test operation. A test receiver receives the test signal through a second pin and a pass gate coupled to the second pin during the boundary scan test operation. A test signal is transmitted to the test receiver during loopback operation through a loopback circuit.

    摘要翻译： 测试驱动器发射器通过电阻终端电路将测试信号驱动到第一引脚，以在边界扫描测试操作期间测试板上的组件。 在边界扫描测试操作期间，测试接收器通过第二引脚和耦合到第二引脚的通过门接收测试信号。 在环回操作期间，通过环回电路将测试信号发送到测试接收机。

    Integrated circuit architectures with heterogeneous high-speed serial interface circuitry
    46.
    发明授权
    Integrated circuit architectures with heterogeneous high-speed serial interface circuitry 有权
    具有异构高速串行接口电路的集成电路架构

    公开(公告)号：US07759972B1

    公开(公告)日：2010-07-20

    申请号：US11981934

    申请日：2007-10-31

    申请人： Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding ,  Thungoc M. Tran ,  Tim Tri Hoang

    发明人： Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding ,  Thungoc M. Tran ,  Tim Tri Hoang

    IPC分类号： H01L25/00

    CPC分类号： H03K19/177

    摘要： An integrated circuit device such as a programmable logic device (“PLD”) includes a plurality of blocks of legacy circuitry. These legacy blocks leave at least one corner of the device unoccupied by such legacy circuitry. This at least one corner is used for relatively newly developed circuitry so as to simplify and speed the design of relatively new circuitry, to avoid having to significantly redesign any of the legacy circuitry to give the device the capabilities of the new circuitry, etc. The relatively newly developed circuitry may be high-speed serial data signal interface (“HSSI”) circuitry that is capable of operating at serial data rates faster than any legacy HSSI circuitry on the device.

    摘要翻译： 诸如可编程逻辑器件（“PLD”）的集成电路器件包括多个遗留电路块。 这些传统块离开设备的至少一个角落，不被这种遗留电路占用。 这个至少一个角用于相对新开发的电路，以便简化和加速相对新的电路的设计，以避免必须重新设计任何传统电路以给予设备新电路的能力等。 相对新开发的电路可以是高速串行数据信号接口（“HSSI”）电路，其能够以比设备上的任何传统HSSI电路更快的串行数据速率工作。

    Signal amplitude detection circuitry without pattern dependencies for high-speed serial links
    47.
    发明授权
    Signal amplitude detection circuitry without pattern dependencies for high-speed serial links 有权
    信号幅度检测电路，无高速串行链路的模式相关性

    公开(公告)号：US07576570B1

    公开(公告)日：2009-08-18

    申请号：US11508607

    申请日：2006-08-22

    申请人： Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

    发明人： Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat ,  Thungoc M. Tran ,  Tim Tri Hoang

    IPC分类号： H03K5/153

    CPC分类号： H03K5/153 ,  H03K5/24

    摘要： Precision amplitude detection circuitry without pattern dependencies is provided that includes rectifier circuitry to output a rectified voltage signal and delay circuitry to send one or more delayed or phase-shifted versions of a differential signal input to the rectifier circuitry. The delayed versions of the differential signal input may be delayed in order to reduce or eliminate the dips in the input seen by the rectifier. This may help correct for low rectified voltage levels. The signal amplitude detection circuitry of the present invention may be incorporated on the input pin of any programmable logic resource and may be included in communication circuitry of a PLD. The precision amplitude detection circuitry may operate in the Gbps (gigabit per second) range.

    摘要翻译： 提供了没有图形相关性的精密幅度检测电路，其包括整流电路，用于输出整流电压信号和延迟电路，以将一个或多个差分信号输入的延迟或相移版本发送到整流器电路。 可以延迟差分信号输入的延迟版本，以便减少或消除由整流器看到的输入中的下降。 这可能有助于校正低整流电压电平。 本发明的信号幅度检测电路可以结合在任何可编程逻辑资源的输入引脚上，并且可以被包括在PLD的通信电路中。 精度幅度检测电路可以以Gbps（千兆位/秒）范围工作。

    Dynamic bias circuit
    48.
    发明授权
    Dynamic bias circuit 有权
    动态偏置电路

    公开(公告)号：US07414559B2

    公开(公告)日：2008-08-19

    申请号：US11735113

    申请日：2007-04-13

    申请人： Tin Lai ,  Wilson Wong ,  Sergey Yurevich Shumarayev

    发明人： Tin Lai ,  Wilson Wong ,  Sergey Yurevich Shumarayev

    IPC分类号： H03M1/66

    CPC分类号： G11C7/12 ,  G11C7/1045 ,  H03M1/662

    摘要： A bias circuit includes a digital to analog converter (D2A) generating an output representing a voltage level for tuning an analog signal. The D2A is coupled to a primary register frame that is one of a plurality of register frames forming a data chain. The plurality of register frames are serially linked and data within the data chain is shifted among the plurality of register frames. Through a time domain multiplexing scheme, the D2A can be shared by control knobs of the equalization circuit. The bias circuit includes a decoder also coupled to the primary register frame. An output enable logic module is also included. The output enable logic module determines when the primary register has a complete data set as the data within the data chain is shifting according to the clock period. A method for adjusting a signal through a bias circuit is also provided.

    摘要翻译： 偏置电路包括产生表示用于调谐模拟信号的电压电平的输出的数模转换器（D 2A）。 D 2 A耦合到作为形成数据链的多个寄存器帧之一的主寄存器帧。 多个寄存器帧被串行链接，数据链内的数据在多个寄存器帧之间移位。 通过时域复用方案，D 2 A可由均衡电路的控制旋钮共享。 偏置电路包括还耦合到主寄存器框架的解码器。 还包括一个输出使能逻辑模块。 当数据链中的数据根据​​时钟周期进行移位时，输出使能逻辑模块确定主寄存器何时具有完整的数据集。 还提供了一种通过偏置电路调整信号的方法。

    Signal offset cancellation
    49.
    发明授权
    Signal offset cancellation 有权
    信号偏移消除

    公开(公告)号：US07368968B1

    公开(公告)日：2008-05-06

    申请号：US11323372

    申请日：2005-12-29

    申请人： Tin H. Lai ,  Wilson Wong

    发明人： Tin H. Lai ,  Wilson Wong

    IPC分类号： H03F3/45 ,  H03L5/00

    CPC分类号： H03F3/45475 ,  H03F3/45192 ,  H03F3/45744 ,  H03F3/45968 ,  H03F2200/321 ,  H03F2203/45212 ,  H03F2203/45646 ,  H03F2203/45678 ,  H03F2203/45681 ,  H03F2203/45726

    摘要： Techniques and circuitry are provided for programmably controlling signal offsets in integrated circuitry. In one embodiment, an integrated circuit includes a signal offset cancellation circuit that is programmably selected to control the offset of signals on either one input/output or another input/output of an amplifier circuit. In one embodiment, a logic circuit is used to selectively couple a bank of current sources to one input/output or another input/output of a differential amplifier through a switching circuit. The bank of current sources may employed to control the signal offset on either input/output, or may be decoupled from all of the inputs/outputs when signal offset cancellation is not required.

    摘要翻译： 提供技术和电路用于可编程地控制集成电路中的信号偏移。 在一个实施例中，集成电路包括可编程地选择以控制放大器电路的一个输入/输出或另一个输入/输出上的信号的偏移的信号偏移消除电路。 在一个实施例中，逻辑电路用于通过开关电路将一组电流源选择性地耦合到差分放大器的一个输入/输出或另一个输入/输出。 可以采用电流源的组来控制输入/输出上的信号偏移，或者当不需要信号偏移消除时可以与所有的输入/输出去耦。