Including descriptor queue empty events in completion events
    41.
    发明授权
    Including descriptor queue empty events in completion events 有权
    在完成事件中包括描述符队列空事件

    公开(公告)号:US07831749B2

    公开(公告)日:2010-11-09

    申请号:US11050474

    申请日:2005-02-03

    CPC classification number: G06F9/4812 G06F13/28 G06F13/32 G06F13/385

    Abstract: Roughly described, method for managing data transmission between a host subsystem and a network interface device, in which the host writes data buffer descriptors into a DMA descriptor queue, and the network interface device writes completion events to notify the host when it has completed processing of data buffers. Each of the completion event descriptors notify the host of completion of data transfer between the NIC and one or more of the data buffers, and can also embed a queue empty notification inside the completion event.

    Abstract translation: 大体描述了用于管理主机子系统和网络接口设备之间的数据传输的方法,其中主机将数据缓冲器描述符写入DMA描述符队列,并且网络接口设备写入完成事件以在主机完成处理 数据缓冲区。 每个完成事件描述符通知主机NIC和一个或多个数据缓冲区之间的数据传输完成,并且还可以在完成事件中嵌入队列空通知。

    Over-current protection device
    42.
    发明申请
    Over-current protection device 审中-公开
    过电流保护装置

    公开(公告)号:US20050128046A1

    公开(公告)日:2005-06-16

    申请号:US11000788

    申请日:2004-12-01

    Applicant: Zack Lin Ching Yu

    Inventor: Zack Lin Ching Yu

    CPC classification number: H01C1/148 H01C7/027

    Abstract: An over-current protection device includes a current-sensitive element, two insulating layers and two electrode layers. The current-sensitive element comprises two electrode foils and a current-sensitive layer laminated between the two electrode foils, where the current-sensitive layer has the behavior of positive temperature coefficient. The two insulating layers are stacked on the upper and lower surfaces of the current-sensitive element, respectively, and the glass switching temperature thereof is between 90-120° C. or the heat dissipation rate is between 1-7W/° C.-m. The two electrode layers are connected to the two ends of the current-sensitive element, respectively.

    Abstract translation: 过流保护装置包括电流敏感元件,两个绝缘层和两个电极层。 电流敏感元件包括两个电极箔和层压在两个电极箔之间的电流敏感层,其中电流敏感层具有正温度系数的行为。 两个绝缘层分别堆叠在电流敏感元件的上表面和下表面上,玻璃切换温度在90-120℃之间或散热率在1-7W /℃之间。 m。 两个电极层分别连接到电流敏感元件的两端。

    Over-current protection device and manufacturing method thereof
    43.
    发明申请
    Over-current protection device and manufacturing method thereof 有权
    过流保护装置及其制造方法

    公开(公告)号:US20050094347A1

    公开(公告)日:2005-05-05

    申请号:US10978856

    申请日:2004-11-01

    Applicant: Zack Lin Ching Yu

    Inventor: Zack Lin Ching Yu

    CPC classification number: H01C1/08 H01C1/1406 H01C7/02

    Abstract: An over-current protection device comprises at least one PTC component, at least one thermal dissipation layer, at least one adhesive layer and at least two isolation layers, wherein the PTC component is formed by interposing a PTC material between two electrode layers. The at least one adhesive layer as a thermal conductive medium is interposed between the PTC component and at least one thermal dissipation layer to combine them. The at least two isolation layers separate the thermal dissipation layer, adhesive layer and electrode layers into two electrical independent portions.

    Abstract translation: 过电流保护装置包括至少一个PTC部件,至少一个散热层,至少一个粘合剂层和至少两个隔离层,其中PTC部件通过在两个电极层之间插入PTC材料形成。 作为导热介质的至少一个粘合剂层插入在PTC部件和至少一个散热层之间以将它们组合。 至少两个隔离层将散热层,粘合剂层和电极层分成两个电独立部分。

    Generic register interface for accessing registers located in different clock domains
    45.
    发明授权
    Generic register interface for accessing registers located in different clock domains 有权
    用于访问位于不同时钟域的寄存器的通用寄存器接口

    公开(公告)号:US06721277B1

    公开(公告)日:2004-04-13

    申请号:US09321086

    申请日:1999-05-28

    CPC classification number: G06F1/12 H04L7/02

    Abstract: A novel method of providing an external host processor with access to registers located in different clock domains. The method comprises the steps of translating host processor interface signals into internal register interface signals, and performing handshaking with the registers via the internal register interface. The handshaking includes supplying registers with a register access signal for enabling access to a selected register, and producing a register ready signal in response to the register access signal. Synchronization signals delayed with respect to the register ready signal may be used for synchronizing registers located in different clock domains with the processor interface.

    Abstract translation: 提供外部主机处理器访问位于不同时钟域中的寄存器的新颖方法。 该方法包括将主机处理器接口信号转换成内部寄存器接口信号,并通过内部寄存器接口与寄存器执行握手的步骤。 握手包括向寄存器提供寄存器访问信号以使得能够访问所选择的寄存器,并且响应于寄存器访问信号产生寄存器就绪信号。 相对于寄存器就绪信号延迟的同步信号可以用于与处理器接口同步位于不同时钟域的寄存器。

    Freezing mechanism for debugging
    46.
    发明授权
    Freezing mechanism for debugging 有权
    冻结机制进行调试

    公开(公告)号:US06389557B1

    公开(公告)日:2002-05-14

    申请号:US09154077

    申请日:1998-09-16

    CPC classification number: G06F11/2236

    Abstract: A system for freezing a communication device in a debug mode has a clock control circuit arranged to produce an internal clock signal in response to an external clock signal. When a stop signal is asserted, the internal clock signal is fixed in its off state. As a result, operations of internal registers supplied with the internal clock signal freeze in a chosen state. A scan test may be performed to examine the internal registers in the chosen state. A bypass clock signal is supplied to control the internal clock signal so as to move the internal registers from one state to another. Thus, an event that causes an error may be recreated.

    Abstract translation: 用于在调试模式下冻结通信设备的系统具有时钟控制电路,其被布置为响应于外部时钟信号产生内部时钟信号。 当停止信号被置位时,内部时钟信号被固定在其关闭状态。 结果,内部时钟信号提供的内部寄存器的操作在选定状态下冻结。 可以执行扫描测试以检查所选状态下的内部寄存器。 提供旁路时钟信号来控制内部时钟信号,以便将内部寄存器从一个状态移动到另一个状态。 因此,可能会重新创建导致错误的事件。

    Programming the size of a broad-specific boot ROM
    47.
    发明授权
    Programming the size of a broad-specific boot ROM 失效
    编程大容量的特定引导ROM

    公开(公告)号:US06370642B1

    公开(公告)日:2002-04-09

    申请号:US09316180

    申请日:1999-05-21

    CPC classification number: G06F12/0223 G06F12/0653

    Abstract: A system is provided to support programming the size of a board-specific boot ROM in an embedded control system. Depending on functions performed by the embedded control system, a manufacturer decides which storage size of the boot ROM is required. An EEPROM of the embedded system is programmed to represent the selected boot ROM size. A network interface that provides data communications between the embedded control system and a data network has a boot ROM size detection circuit that supports boot ROM size programming. The boot ROM size detection circuit includes a ROM range register programmable from the EEPROM, and a boot ROM base address register programmable by an embedded controller via a PCI bus. During a power up process, the boot ROM size data from the EEPROM are loaded into the ROM range register. The embedded controller writes a predetermined value into the boot ROM base address register so as to read information representing the selected boot ROM size. Based on this information, the embedded controller assigns memory addresses in the network interface for the boot ROM of the selected size.

    Abstract translation: 提供了一种系统,用于支持在嵌入式控制系统中对板特定引导ROM的大小进行编程。 根据嵌入式控制系统执行的功能,制造商决定需要启动ROM的存储大小。 嵌入式系统的EEPROM被编程为表示所选择的引导ROM大小。 在嵌入式控制系统和数据网络之间提供数据通信的网络接口具有支持引导ROM大小编程的引导ROM大小检测电路。 引导ROM大小检测电路包括可从EEPROM编程的ROM范围寄存器,以及通过PCI总线由嵌入式控制器可编程的引导ROM基地址寄存器。 在加电过程中,来自EEPROM的引导ROM大小数据被加载到ROM范围寄存器中。 嵌入式控制器将预定值写入引导ROM基地址寄存器,以便读取表示所选引导ROM大小的信息。 基于该信息,嵌入式控制器为所选大小的引导ROM分配网络接口中的存储器地址。

    Interrupt management system having batch mechanism for handling
interrupt events
    48.
    发明授权
    Interrupt management system having batch mechanism for handling interrupt events 有权
    具有处理中断事件的批处理机制的中断管理系统

    公开(公告)号:US6115779A

    公开(公告)日:2000-09-05

    申请号:US234456

    申请日:1999-01-21

    CPC classification number: G06F13/24 G06F2213/2406

    Abstract: An interrupt management system that enables a user to handle interrupt events either in a real time mode of operation, or in a batch mode of operation. In the real time mode, an interrupt request signal is asserted in response to each interrupt event. In the batch mode, an interrupt request signal is delayed until a predetermined number of interrupt events is detected, or until a predetermined time interval has elapsed since the last interrupt event is captured. In response to an interrupt event, the corresponding bit in an interrupt register is set to an active state. A control interrupt bit is provided in an interrupt control register for each interrupt to enable the activation of an interrupt request pin in response to the interrupt event. A batch enable bit is provided in a batch register for each interrupt event to enable the batching of the interrupt event.

    Abstract translation: 一种中断管理系统,使用户能够以实时操作模式或批处理操作模式处理中断事件。 在实时模式中,响应于每个中断事件,中断请求信号被断言。 在批处理模式中,中断请求信号被延迟直到检测到预定数量的中断事件,或直到从上一个中断事件被捕获起经过了预定的时间间隔为止。 响应于中断事件,中断寄存器中的相应位被设置为活动状态。 在每个中断的中断控制寄存器中都提供一个控制中断位,以响应中断事件使能中断请求引脚的激活。 在每个中断事件的批处理寄存器中提供了一批批使能位,以使中断事件能够进行批处理。

    Hashing algorithm for network receive filtering
    49.
    发明授权
    Hashing algorithm for network receive filtering 有权
    用于网络接收过滤的哈希算法

    公开(公告)号:US07984180B2

    公开(公告)日:2011-07-19

    申请号:US11255124

    申请日:2005-10-20

    Abstract: Roughly described, a network interface device is assigned a maximum extent-of-search. A hash function is applied to the header information of each incoming packet, to generate a hash code for the packet. The hash code designates a particular subset of the table within which the particular header information should be found, and an iterative search is made within that subset. If the search locates a matching entry before the search limit is exceeded, then the incoming data packet is delivered to the receive queue identified in the matching entry. But if the search reaches the search limit before a matching entry is located, then device delivers the packet to a default queue, such as a kernel queue, in the host computer system. The kernel is then responsible for delivering the packet to the correct endpoint.

    Abstract translation: 大致描述了网络接口设备被分配最大的搜索范围。 散列函数被应用于每个输入分组的报头信息,以产生分组的哈希码。 哈希代码指定在其中应当找到特定头部信息的表的特定子集,并且在该子集内进行迭代搜索。 如果搜索在超出搜索限制之前找到匹配的条目,则传入数据包将被传递到匹配条目中标识的接收队列。 但是,如果在找到匹配的条目之前搜索达到搜索限制,则设备会将数据包传递到主机系统中的默认队列(如内核队列)。 然后,内核负责将数据包传递到正确的端点。

    UPPER INTERNALS ARRANGEMENT FOR A PRESSURIZED WATER REACTOR
    50.
    发明申请
    UPPER INTERNALS ARRANGEMENT FOR A PRESSURIZED WATER REACTOR 有权
    一种加压水反应器的上部内部装置

    公开(公告)号:US20080253497A1

    公开(公告)日:2008-10-16

    申请号:US11733248

    申请日:2007-04-10

    Abstract: In a pressurized water reactor with ail of the in-core instrumentation gaining access to the core through the reactor head, each fuel assembly in which the instrumentation is introduced is aligned with an upper internals instrumentation guide-way. In the elevations above the upper internals upper support assembly, the instrumentation is protected and aligned by upper mounted instrumentation columns that are part of the instrumentation guide-way and extend from the upper support assembly towards the reactor head in hue with a corresponding head penetration. The upper mounted instrumentation columns are supported laterally at one end by an upper guide tube and at the other end by the upper support plate.

    Abstract translation: 在具有核心仪器的一部分的加压水反应器中,通过反应器头进入核心,将引入仪器的每个燃料组件与上部内部仪器仪表导轨对准。 在上部内部上部支撑组件上方的高度中,仪器由作为仪表导向器一部分的上部安装的仪表柱保护和对准,并且从上部支撑组件朝向反应器头部以色调以相应的头部穿透延伸。 上部安装的仪器支架在一端通过上导向管横向支撑,另一端由上支撑板支撑。

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