Abstract:
Roughly described, method for managing data transmission between a host subsystem and a network interface device, in which the host writes data buffer descriptors into a DMA descriptor queue, and the network interface device writes completion events to notify the host when it has completed processing of data buffers. Each of the completion event descriptors notify the host of completion of data transfer between the NIC and one or more of the data buffers, and can also embed a queue empty notification inside the completion event.
Abstract:
An over-current protection device includes a current-sensitive element, two insulating layers and two electrode layers. The current-sensitive element comprises two electrode foils and a current-sensitive layer laminated between the two electrode foils, where the current-sensitive layer has the behavior of positive temperature coefficient. The two insulating layers are stacked on the upper and lower surfaces of the current-sensitive element, respectively, and the glass switching temperature thereof is between 90-120° C. or the heat dissipation rate is between 1-7W/° C.-m. The two electrode layers are connected to the two ends of the current-sensitive element, respectively.
Abstract:
An over-current protection device comprises at least one PTC component, at least one thermal dissipation layer, at least one adhesive layer and at least two isolation layers, wherein the PTC component is formed by interposing a PTC material between two electrode layers. The at least one adhesive layer as a thermal conductive medium is interposed between the PTC component and at least one thermal dissipation layer to combine them. The at least two isolation layers separate the thermal dissipation layer, adhesive layer and electrode layers into two electrical independent portions.
Abstract:
A network switch having switch ports for communication of data packets with respective computer network nodes according to CSMA/CD protocol that resets a retry counter within any one of the respective switch ports if backpressure is asserted by that port. The resetting of the retry counter within a port after assertion of backpressure affords the port a greater probability of winning collision mediation under the CSMA/CD protocol, thus more quickly relieving congestion which may occur in the network switch.
Abstract:
A novel method of providing an external host processor with access to registers located in different clock domains. The method comprises the steps of translating host processor interface signals into internal register interface signals, and performing handshaking with the registers via the internal register interface. The handshaking includes supplying registers with a register access signal for enabling access to a selected register, and producing a register ready signal in response to the register access signal. Synchronization signals delayed with respect to the register ready signal may be used for synchronizing registers located in different clock domains with the processor interface.
Abstract:
A system for freezing a communication device in a debug mode has a clock control circuit arranged to produce an internal clock signal in response to an external clock signal. When a stop signal is asserted, the internal clock signal is fixed in its off state. As a result, operations of internal registers supplied with the internal clock signal freeze in a chosen state. A scan test may be performed to examine the internal registers in the chosen state. A bypass clock signal is supplied to control the internal clock signal so as to move the internal registers from one state to another. Thus, an event that causes an error may be recreated.
Abstract:
A system is provided to support programming the size of a board-specific boot ROM in an embedded control system. Depending on functions performed by the embedded control system, a manufacturer decides which storage size of the boot ROM is required. An EEPROM of the embedded system is programmed to represent the selected boot ROM size. A network interface that provides data communications between the embedded control system and a data network has a boot ROM size detection circuit that supports boot ROM size programming. The boot ROM size detection circuit includes a ROM range register programmable from the EEPROM, and a boot ROM base address register programmable by an embedded controller via a PCI bus. During a power up process, the boot ROM size data from the EEPROM are loaded into the ROM range register. The embedded controller writes a predetermined value into the boot ROM base address register so as to read information representing the selected boot ROM size. Based on this information, the embedded controller assigns memory addresses in the network interface for the boot ROM of the selected size.
Abstract:
An interrupt management system that enables a user to handle interrupt events either in a real time mode of operation, or in a batch mode of operation. In the real time mode, an interrupt request signal is asserted in response to each interrupt event. In the batch mode, an interrupt request signal is delayed until a predetermined number of interrupt events is detected, or until a predetermined time interval has elapsed since the last interrupt event is captured. In response to an interrupt event, the corresponding bit in an interrupt register is set to an active state. A control interrupt bit is provided in an interrupt control register for each interrupt to enable the activation of an interrupt request pin in response to the interrupt event. A batch enable bit is provided in a batch register for each interrupt event to enable the batching of the interrupt event.
Abstract:
Roughly described, a network interface device is assigned a maximum extent-of-search. A hash function is applied to the header information of each incoming packet, to generate a hash code for the packet. The hash code designates a particular subset of the table within which the particular header information should be found, and an iterative search is made within that subset. If the search locates a matching entry before the search limit is exceeded, then the incoming data packet is delivered to the receive queue identified in the matching entry. But if the search reaches the search limit before a matching entry is located, then device delivers the packet to a default queue, such as a kernel queue, in the host computer system. The kernel is then responsible for delivering the packet to the correct endpoint.
Abstract:
In a pressurized water reactor with ail of the in-core instrumentation gaining access to the core through the reactor head, each fuel assembly in which the instrumentation is introduced is aligned with an upper internals instrumentation guide-way. In the elevations above the upper internals upper support assembly, the instrumentation is protected and aligned by upper mounted instrumentation columns that are part of the instrumentation guide-way and extend from the upper support assembly towards the reactor head in hue with a corresponding head penetration. The upper mounted instrumentation columns are supported laterally at one end by an upper guide tube and at the other end by the upper support plate.