Semiconductor memory device
    42.
    发明授权

    公开(公告)号:US5943275A

    公开(公告)日:1999-08-24

    申请号:US181787

    申请日:1998-10-28

    申请人: Haruki Toda

    发明人: Haruki Toda

    摘要: It is an object of this invention to provide a semiconductor memory device in which a failure can be efficiently remedied even for a larger number of bits. In a multi-bit memory capable of simultaneously exchanging a plurality of data upon reception of an address, spare DQ lines (15c) commonly used for each I/O, a spare sense amplifier circuit (13c), a spare column switch (14c), a fuse box (20) for storing the address of a DQ line in which a failure has occurred, and fuse circuits (21-1, 21-2, . . . ) for storing an I/O to which the failure-DQ line belongs are arranged to remedy the failure for each I/O. Since only a memory cell belonging to one I/O where a failure has occurred is replaced, unnecessary replacement is not executed, and the memory cell can be efficiently remedied even for a larger number of bits.

    Clock-synchronous semiconductor memory device
    43.
    发明授权
    Clock-synchronous semiconductor memory device 失效
    时钟同步半导体存储器件

    公开(公告)号:US5818793A

    公开(公告)日:1998-10-06

    申请号:US457165

    申请日:1995-06-01

    IPC分类号: G11C7/10 G11C8/04 G11C7/00

    摘要: A clock-synchronous semiconductor memory device includes many memory cells arranged in matrix, a count section for counting the actual number of cycles of a continuous, externally-supplied basic clock signal, a control section for inputting a row enable control signal (/RE) and the column enable control signal (/CE) provided from an external device, other than the basic clock signal, for which the control signals are at a specified level, synchronized with the basic control signal, and for setting the initial address for data access of the memory cells, and a data I/O section for executing a data access operation for the address set by the control section. In the device, the output of data from the memory cells through the data I/O means is started after the setting of the initial address by the control sections and after a specified number of basic clock signals has been counted by the count section.

    摘要翻译: 时钟同步半导体存储器件包括以矩阵形式布置的许多存储器单元,用于对连续的外部供给的基本时钟信号的实际循环次数进行计数的计数部分,用于输入行使能控制信号(/ RE)的控制部分, 以及与基本时钟信号不同的外部设备提供的与基本控制信号同步的指令级别的列使能控制信号(/ CE),并且用于设置用于数据访问的初始地址 以及用于执行由控制部分设置的地址的数据访问操作的数据I / O部分。 在该设备中,通过控制部分设置初始地址之后并且在计数部分计数了指定数量的基本时钟信号之后,通过数据I / O装置从存储器单元输出数据。

    Multiport field memory
    44.
    发明授权
    Multiport field memory 失效
    多端口字段内存

    公开(公告)号:US5708618A

    公开(公告)日:1998-01-13

    申请号:US658312

    申请日:1996-06-05

    摘要: A multiport field memory includes cell arrays, bit line pairs, gate transmission circuits connecting to the bit line pairs, ports, and a data cross-transmission circuit. The data cross-transmission circuit has first and second transfer gate circuit pairs (each pair connected in series and each pair connected to each bit line pair). The ports, each includes a register for temporarily storing data and for transferring the data from or to the memory cell through the bit line pairs. Each port is connected to each bit line pair through each first and second transfer gate circuit pair. The data cross-transmission control circuit has the first and second transfer gate control circuit pairs to transfer first and second gate drive control signals in order to connect the bit line pair to the registers. The first transfer gate circuit in one pair of the first and second transfer gate circuit pairs is connected to the second transfer gate circuit in the same pair or another pair of the first and second transfer gate circuit pairs in order to transfer the data through a desired port under the control of the cross-transmission control circuit.

    摘要翻译: 多端口场存储器包括单元阵列,位线对,连接到位线对的栅极传输电路,端口和数据交叉传输电路。 数据交叉传输电路具有第一和第二传输门电路对(每对串联连接,每对连接到每个位线对)。 端口各自包括用于临时存储数据并通过位线对将数据从存储器单元传送到存储器单元的寄存器。 每个端口通过每个第一和第二传输门电路对连接到每个位线对。 数据交叉传输控制电路具有第一和第二传输门控制电路对以传送第一和第二栅极驱动控制信号,以将位线对连接到寄存器。 一对第一和第二传输门电路对中的第一传输门电路连接到同一对或另一对第一和第二传输门电路对中的第二传输门电路,以便通过期望的 端口在交叉传输控制电路的控制下。

    Data transfer system
    45.
    发明授权
    Data transfer system 失效
    数据传输系统

    公开(公告)号:US5706248A

    公开(公告)日:1998-01-06

    申请号:US751023

    申请日:1996-11-15

    申请人: Haruki Toda

    发明人: Haruki Toda

    IPC分类号: G11C7/10 G11C8/04

    CPC分类号: G11C7/1006 G11C7/103

    摘要: A data transfer system, comprising: a plurality of data input/output gates arranged by k-unit group by k-unit group in a predetermined sequence; gate selecter circuit each arranged for k-unit group of the gates, for selecting the gates in unit of k-unit group; a plurality of data transfer paths for transferring data via the gates selected by the gate selecting means; a first register group composed of a-units of data registers for transferring data simultaneously to and from the data transfer paths, the a-unit data registers being serial-accessed in a constant sequence; and a scrambler circuit for designating any required data input/output gates and for further selectively connecting the data transfer paths connected to said designated data input/output gates with the data registers so that the data transfer paths connected to the designated input/output gates can be connected to the serial-accessible registers in a predetermined sequence, when the number of the data transfer paths is (L.times.k) under the following conditions: if a (mod k).ident.0, 1, L=�a/k!+1 if other than the above, L=�a/k!+2 where L denotes a maximum number of the gate selecting means selectable simultaneously.

    摘要翻译: 一种数据传输系统,包括:以预定顺序由k-单元组以k-单元组排列的多个数据输入/输出门; 每个栅极选择器电路均设置用于k单元组的栅极,用于以k单元组为单位选择栅极; 用于经由门选择装置选择的门传送数据的多个数据传送路径; 由数据寄存器组成的第一寄存器组,用于同时传送数据传输路径和从数据传输路径传输数据,该单位数据寄存器以恒定顺序串行访问; 以及加扰电路,用于指定任何所需的数据输入/输出门,并且用于进一步选择性地将连接到所述指定的数据输入/输出门的数据传送路径与数据寄存器连接,使得连接到指定的输入/输出门的数据传送路径 在以下条件下,当数据传输路径的数量为(Lxk)时,以预定的顺序连接到可串行访问的寄存器:如果(mod k)= 0,1,L = [a / k] + 1if 除了上述之外,L = [a / k] + 2其中L表示同时选择的选通选择装置的最大数目。

    Multi-bank synchronous memory system with cascade-type memory cell
structure
    46.
    发明授权
    Multi-bank synchronous memory system with cascade-type memory cell structure 失效
    具有级联型存储单元结构的多行同步存储器系统

    公开(公告)号:US5689473A

    公开(公告)日:1997-11-18

    申请号:US690479

    申请日:1996-07-31

    申请人: Haruki Toda

    发明人: Haruki Toda

    摘要: A synchronous memory system with a cascade-type memory cell structure has memory cells having a cascade type construction (or NAND type configuration), a row decoder, save registers, a sense amplifier, and a selector. The selector transmits a control signal to halt a sense operation for the memory cells when the sense operation for a target memory cell to be accessed in completed. The row decoder includes a decoder for decoding a row address, a latch circuit, a word line driver. The latch circuit stores a result of a decode operation, and the word line driver comprises a PMOS transistor and a NMOS transistor connected in series. A 8 volt power (Vpp) is supplied to the PMOS transistor in the word line driver.

    摘要翻译: 具有级联型存储单元结构的同步存储器系统具有具有级联类型结构(或NAND类型配置),行解码器,存储寄存器,读出放大器和选择器的存储器单元。 当完成要访问的目标存储器单元的感测操作时,选择器发送控制信号以停止对存储器单元的感测操作。 行解码器包括用于解码行地址的解码器,锁存电路,字线驱动器。 锁存电路存储解码操作的结果,字线驱动器包括串联连接的PMOS晶体管和NMOS晶体管。 8 V功率(Vpp)被提供给字线驱动器中的PMOS晶体管。

    Semiconductor memory device
    47.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号:US5612925A

    公开(公告)日:1997-03-18

    申请号:US463394

    申请日:1995-06-05

    摘要: A semiconductor memory device, including a memory cell array having a plurality of memory cells arranged in rows and columns, the memory cells storing data and being selected according to address signals. The device includes a control unit which receives a clock signal and a first control, or trigger, signal for outputting a plurality of the data in synchronism with the clock signal after the first control signal is asserted. The output of the data beginning after a number of clock cycles (N) of the clock signal (N being a positive integer .gtoreq.2) after the first control signal is asserted, a different one of the data being output at each of the clock cycles after the output begins until the plurality of data is output.

    摘要翻译: 一种半导体存储器件,包括具有以行和列排列的多个存储单元的存储单元阵列,存储单元存储数据并根据地址信号进行选择。 该装置包括控制单元,该控制单元接收时钟信号和用于在第一控制信号被断言之后与时钟信号同步地输出多个数据的第一控制或触发信号。 在第一控制信号被断言之后的时钟信号(N为正整数> / = 2)的多个时钟周期(N)之后开始的数据的输出,在每个 在输出开始直到输出多个数据之后的时钟周期。

    Semiconductor memory device
    48.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号:US5508970A

    公开(公告)日:1996-04-16

    申请号:US345682

    申请日:1994-11-21

    申请人: Haruki Toda

    发明人: Haruki Toda

    摘要: A semiconductor memory device having a memory cell array (MCA) composed of a plurality of memory cells arranged in a matrix pattern including a plurality of columns, a data register section provided with two first and second registers each having "a"-units of one-bit data register; a control section for selecting two sets of "a"-units of the column from a plurality of the columns for each "a"-cycles in accordance with inputted and read addresses, and for storing the "a"-units of data of the selected 2 "a"-units of column in either one of the first and second registers alternately on the basis of a sequence of the read addresses; and a data output section for scanning and outputting data of the 2 "a"-units of the one-bit data register in sequence. Data of column bits more than the number of the registers can be accessed continuously in spite of the minimum register configuration. Further, the head column address can be selected freely.

    摘要翻译: 一种具有存储单元阵列(MCA)的半导体存储器件,具有以包括多列的矩阵模式布置的多个存储单元组成的数据寄存器单元,具有两个第一和第二寄存器,每个寄存器具有“a” - 一个单位 位数据寄存器; 控制部分,用于根据输入和读取的地址从每个“a”的多个列中选择列的两组“a”组,并且用于存储“a” 根据读取地址的顺序交替地选择第一和第二寄存器中的任一个寄存器中的列“2”一个“一列” 以及数据输出部分,用于依次扫描和输出一位数据寄存器的2“a”个数据的数据。 尽管最小的寄存器配置,列位数大于寄存器数量的数据可以连续访问。 此外,可以自由选择头列地址。

    Clock-synchronous semiconductor memory device and method for accessing
the device
    49.
    发明授权
    Clock-synchronous semiconductor memory device and method for accessing the device 失效
    时钟同步半导体存储器件和用于访问器件的方法

    公开(公告)号:US5323358A

    公开(公告)日:1994-06-21

    申请号:US024354

    申请日:1993-03-01

    CPC分类号: G11C8/18 G11C7/22

    摘要: A method for accessing a clock-synchronous semiconductor memory device including memory cells arranged in matrix. The cells are divided into at least two blocks, access to the cells in these blocks is designated from address data provided from an external device, and access to the memory cell is executed synchronously with an externally-supplied clock signal, which comprises setting the other blocks in an access preparation state or in an access operation standby state while one block is in an access operating state, setting a certain block in the access operating state via the access preparation state when the certain block is designated for the access operation by the address data and if the certain block is in the access operating state, and setting a certain block in the access operating state immediately when the certain block is designated for the access operation by the address data and if the certain block is in the access preparation state or in the access operation standby state. In the device, the designation of the cell in the block to be accessed is set using address data designating a block externally-provided from outside of the device.

    摘要翻译: 一种用于访问包括以矩阵布置的存储单元的时钟同步半导体存储器件的方法。 单元被划分为至少两个块,从外部设备提供的地址数据指定对这些块中的单元的访问,并且与外部提供的时钟信号同步地执行对存储单元的访问,其中包括设置另一个 在一个块处于访问操作状态时处于访问准备状态或访问操作待机状态的块,当通过地址指定特定块进行访问操作时,经由访问准备状态将某个块设置在访问操作状态 数据,并且如果某个块处于访问操作状态,并且当特定块被地址数据指定用于访问操作时,并且特定块处于访问准备状态时,立即将某个块设置在访问操作状态,或者 在访问操作待机状态。 在设备中,使用指定从设备外部提供的块的地址数据来设置要访问的块中的小区的指定。

    Image memory
    50.
    发明授权
    Image memory 失效
    图像存储器

    公开(公告)号:US5185724A

    公开(公告)日:1993-02-09

    申请号:US586232

    申请日:1990-09-21

    申请人: Haruki Toda

    发明人: Haruki Toda

    CPC分类号: G11C7/1075

    摘要: An image memory comprises a random access memory, a serial access memory including a main register and a preregister, a data transfer section for carrying out data transfer between the random access memory and the serial access memory, and a designation section for designating an address of serial access. The data transfer section serves to transfer data from the random access memory to the main register of the serial access memory through the preregister. Furthermore, a serial access to the serial access memory is made on the basis of an address designated by the designation means. Thus, a transfer system defined as a hidden transfer for carrying out data transfer only between the random access memory and the preregister is set as a technique for relaxing the restriction on the transfer timings. This technique permits the serial access memory to be used with the divided or split segments having arbitrary lengths, respectively.