摘要:
A semiconductor device for inputting/outputting data in synchronism with a reference clock signal and an internal clock signal in each circuit. In this device, a variably delay section delays a generated clock signal to output an internal clock signal, and a phase error-detecting section detects a time difference between the internal clock signal and the reference clock signal, thereby controlling the delay amount of the variable delay section to make the time difference substantially zero.
摘要:
It is an object of this invention to provide a semiconductor memory device in which a failure can be efficiently remedied even for a larger number of bits. In a multi-bit memory capable of simultaneously exchanging a plurality of data upon reception of an address, spare DQ lines (15c) commonly used for each I/O, a spare sense amplifier circuit (13c), a spare column switch (14c), a fuse box (20) for storing the address of a DQ line in which a failure has occurred, and fuse circuits (21-1, 21-2, . . . ) for storing an I/O to which the failure-DQ line belongs are arranged to remedy the failure for each I/O. Since only a memory cell belonging to one I/O where a failure has occurred is replaced, unnecessary replacement is not executed, and the memory cell can be efficiently remedied even for a larger number of bits.
摘要:
A clock-synchronous semiconductor memory device includes many memory cells arranged in matrix, a count section for counting the actual number of cycles of a continuous, externally-supplied basic clock signal, a control section for inputting a row enable control signal (/RE) and the column enable control signal (/CE) provided from an external device, other than the basic clock signal, for which the control signals are at a specified level, synchronized with the basic control signal, and for setting the initial address for data access of the memory cells, and a data I/O section for executing a data access operation for the address set by the control section. In the device, the output of data from the memory cells through the data I/O means is started after the setting of the initial address by the control sections and after a specified number of basic clock signals has been counted by the count section.
摘要:
A multiport field memory includes cell arrays, bit line pairs, gate transmission circuits connecting to the bit line pairs, ports, and a data cross-transmission circuit. The data cross-transmission circuit has first and second transfer gate circuit pairs (each pair connected in series and each pair connected to each bit line pair). The ports, each includes a register for temporarily storing data and for transferring the data from or to the memory cell through the bit line pairs. Each port is connected to each bit line pair through each first and second transfer gate circuit pair. The data cross-transmission control circuit has the first and second transfer gate control circuit pairs to transfer first and second gate drive control signals in order to connect the bit line pair to the registers. The first transfer gate circuit in one pair of the first and second transfer gate circuit pairs is connected to the second transfer gate circuit in the same pair or another pair of the first and second transfer gate circuit pairs in order to transfer the data through a desired port under the control of the cross-transmission control circuit.
摘要:
A data transfer system, comprising: a plurality of data input/output gates arranged by k-unit group by k-unit group in a predetermined sequence; gate selecter circuit each arranged for k-unit group of the gates, for selecting the gates in unit of k-unit group; a plurality of data transfer paths for transferring data via the gates selected by the gate selecting means; a first register group composed of a-units of data registers for transferring data simultaneously to and from the data transfer paths, the a-unit data registers being serial-accessed in a constant sequence; and a scrambler circuit for designating any required data input/output gates and for further selectively connecting the data transfer paths connected to said designated data input/output gates with the data registers so that the data transfer paths connected to the designated input/output gates can be connected to the serial-accessible registers in a predetermined sequence, when the number of the data transfer paths is (L.times.k) under the following conditions: if a (mod k).ident.0, 1, L=�a/k!+1 if other than the above, L=�a/k!+2 where L denotes a maximum number of the gate selecting means selectable simultaneously.
摘要:
A synchronous memory system with a cascade-type memory cell structure has memory cells having a cascade type construction (or NAND type configuration), a row decoder, save registers, a sense amplifier, and a selector. The selector transmits a control signal to halt a sense operation for the memory cells when the sense operation for a target memory cell to be accessed in completed. The row decoder includes a decoder for decoding a row address, a latch circuit, a word line driver. The latch circuit stores a result of a decode operation, and the word line driver comprises a PMOS transistor and a NMOS transistor connected in series. A 8 volt power (Vpp) is supplied to the PMOS transistor in the word line driver.
摘要:
A semiconductor memory device, including a memory cell array having a plurality of memory cells arranged in rows and columns, the memory cells storing data and being selected according to address signals. The device includes a control unit which receives a clock signal and a first control, or trigger, signal for outputting a plurality of the data in synchronism with the clock signal after the first control signal is asserted. The output of the data beginning after a number of clock cycles (N) of the clock signal (N being a positive integer .gtoreq.2) after the first control signal is asserted, a different one of the data being output at each of the clock cycles after the output begins until the plurality of data is output.
摘要:
A semiconductor memory device having a memory cell array (MCA) composed of a plurality of memory cells arranged in a matrix pattern including a plurality of columns, a data register section provided with two first and second registers each having "a"-units of one-bit data register; a control section for selecting two sets of "a"-units of the column from a plurality of the columns for each "a"-cycles in accordance with inputted and read addresses, and for storing the "a"-units of data of the selected 2 "a"-units of column in either one of the first and second registers alternately on the basis of a sequence of the read addresses; and a data output section for scanning and outputting data of the 2 "a"-units of the one-bit data register in sequence. Data of column bits more than the number of the registers can be accessed continuously in spite of the minimum register configuration. Further, the head column address can be selected freely.
摘要:
A method for accessing a clock-synchronous semiconductor memory device including memory cells arranged in matrix. The cells are divided into at least two blocks, access to the cells in these blocks is designated from address data provided from an external device, and access to the memory cell is executed synchronously with an externally-supplied clock signal, which comprises setting the other blocks in an access preparation state or in an access operation standby state while one block is in an access operating state, setting a certain block in the access operating state via the access preparation state when the certain block is designated for the access operation by the address data and if the certain block is in the access operating state, and setting a certain block in the access operating state immediately when the certain block is designated for the access operation by the address data and if the certain block is in the access preparation state or in the access operation standby state. In the device, the designation of the cell in the block to be accessed is set using address data designating a block externally-provided from outside of the device.
摘要:
An image memory comprises a random access memory, a serial access memory including a main register and a preregister, a data transfer section for carrying out data transfer between the random access memory and the serial access memory, and a designation section for designating an address of serial access. The data transfer section serves to transfer data from the random access memory to the main register of the serial access memory through the preregister. Furthermore, a serial access to the serial access memory is made on the basis of an address designated by the designation means. Thus, a transfer system defined as a hidden transfer for carrying out data transfer only between the random access memory and the preregister is set as a technique for relaxing the restriction on the transfer timings. This technique permits the serial access memory to be used with the divided or split segments having arbitrary lengths, respectively.