公开(公告)号：US07348108B2

公开(公告)日：2008-03-25

申请号：US10938653

申请日：2004-09-10

申请人： Michel L. Cote ,  Christophe Pierrat

发明人： Michel L. Cote ,  Christophe Pierrat

IPC分类号： G03F1/00 ,  G03B27/42

CPC分类号： G03F7/70466 ,  G03F1/26 ,  G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G03F7/70425 ,  G03F7/70433 ,  G03F7/70558

摘要： A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts.

公开(公告)号：US07178128B2

公开(公告)日：2007-02-13

申请号：US10272104

申请日：2002-10-15

申请人： Hua-Yu Liu ,  Christophe Pierrat ,  Kent Richardson

发明人： Hua-Yu Liu ,  Christophe Pierrat ,  Kent Richardson

IPC分类号： G06F17/50

CPC分类号： G03F1/30

摘要： Methods and apparatuses for preparing layouts and masks that use phase shifting to enable production of subwavelength features on an integrated circuit in close (optical) proximity to other structures are described. One embodiment selects from several strategies for resolving conflicts between phase shifters used to define features and (optically) proximate structures that are being defined other than by phase shifting. One embodiment adds additional phase shifters to define the conflicting structures. Another embodiment corrects the shape of the phase shifters in proximity to a conflicting structure. Resulting integrated circuits can include a greater number of subwavelength features even in areas that are in close proximity to structures that were not initially identified for production using a phase shifting mask.

摘要翻译： 描述了用于制备使用相移的布局和掩模的方法和装置，以使得能够在紧密（光学）接近其它结构的集成电路上产生亚波长特征。 一个实施例从用于解决用于定义特征的移相器之间的冲突的几种策略中选择（以光学方式）除了通过相移之外定义的邻近结构之间的冲突。 一个实施例增加了附加移相器来定义冲突结构。 另一个实施例校正了相邻结构附近的移相器的形状。 所得到的集成电路可以包括更多数量的亚波长特征，即使在与初始识别用于使用相移掩模生产的结构非常接近的区域中。

公开(公告)号：US07083879B2

公开(公告)日：2006-08-01

申请号：US09932239

申请日：2001-08-17

申请人： Christophe Pierrat ,  Michel Luc Côté

发明人： Christophe Pierrat ,  Michel Luc Côté

IPC分类号： G03F9/00 ,  G06F17/50

CPC分类号： G03F7/70466 ,  G03F1/26 ,  G03F7/70425 ,  G03F7/70433 ,  G03F7/70558

摘要： A photolithographic mask used for defining a layer in an integrated circuit, or other work piece, where the layer comprises a pattern including a plurality of features to be implemented with phase shifting in phase shift regions is laid out including for patterns comprising high density, small dimension features, and for “full shift” patterns. The method includes identifying cutting areas for phase shift regions based on characteristics of the pattern. Next, the process cuts the phase shift regions in selected ones of the cutting areas to define phase shift windows, and assigns phase values to the phase shift windows. The phase shift values assigned comprise φ and θ, so that destructive interference is caused in transitions between adjacent phase shift windows having respective phase shift values of φ and θ. In the preferred embodiment, φ is equal to approximately θ+180 degrees. Results of the cutting and assigning steps are stored in a computer readable medium, used for manufacturing a mask, and used for manufacturing an integrated circuit. By identifying the cutting areas based on characteristics of the pattern to be formed, the problem of dividing phase shift regions into phase shift windows, and assigning phase shift values to the windows is simplified.

公开(公告)号：US07071058B2

公开(公告)日：2006-07-04

申请号：US10817548

申请日：2004-04-02

申请人： Martin Ceredig Roberts ,  Christophe Pierrat

发明人： Martin Ceredig Roberts ,  Christophe Pierrat

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L27/10855 ,  H01L28/91

摘要： Capacitors, DRAM circuitry, and methods of forming the same are described. In one embodiment, a capacitor comprises a first container which is joined with a substrate node location and has an opening defining a first interior area. A second container is joined with the node location and has an opening defining a second interior area. The areas are spaced apart from one another in a non-overlapping relationship. A dielectric layer and a conductive capacitor electrode layer are disposed operably proximate the first and second containers. In another embodiment, the first and second containers are generally elongate and extend away from the node location along respective first and second central axes. The axes are different and spaced apart from one another. In yet another embodiment, a conductive layer of material is disposed over and in electrical communication with a substrate node location. The layer of material has an outer surface with a first region and a second region spaced apart from the first region. A first container is formed over and in electrical communication with the first region and a second container is formed over and in electrical communication with the second region. In yet another embodiment, the first and second containers define container volumes which are discrete and separated from one another.

摘要翻译： 描述了电容器，DRAM电路及其形成方法。 在一个实施例中，电容器包括与衬底节点位置连接并具有限定第一内部区域的开口的第一容器。 第二容器与节点位置连接并且具有限定第二内部区域的开口。 这些区域以不重叠的关系彼此间隔开。 电介质层和导电电容器电极层可操作地设置在第一和第二容器的附近。 在另一个实施例中，第一和第二容器通常是细长的并且沿相应的第一和第二中心轴线远离节点位置延伸。 轴是不同的并且彼此间隔开。 在另一个实施例中，材料的导电层设置在衬底节点位置上并与衬底节点位置电连通。 材料层具有外表面，其具有第一区域和与第一区域间隔开的第二区域。 第一容器形成在第一区域之上并与第一区域电连通，并且第二容器形成在第二区域上并与第二区域电连通。 在另一个实施例中，第一和第二容器限定彼此离散和分离的容器体积。

公开(公告)号：US07052617B2

公开(公告)日：2006-05-30

申请号：US10318021

申请日：2002-12-13

申请人： Karen Huang ,  Christophe Pierrat

发明人： Karen Huang ,  Christophe Pierrat

IPC分类号： H01L21/302

CPC分类号： H01J9/24 ,  H01J9/025 ,  H01J29/481 ,  H01J31/127

摘要： A process for producing multiple undercut profiles in a single material. A resist pattern is applied over a work piece and a wet etch is performed to produce an undercut in the material. This first wet etch is followed by a polymerizing dry etch that produces a polymer film in the undercut created by the first wet etch. The polymer film prevents further etching of the undercut portion during a second wet etch. Thus, an undercut profile can be obtained having a larger undercut in an underlying portion of the work piece, utilizing only a single resist application step. The work piece may be a multi-layer work piece having different layers formed of the same material, or it may be a single layer of material.

摘要翻译： 用于在单一材料中生产多个底切轮廓的方法。 将抗蚀剂图案施加在工件上，并进行湿蚀刻以在材料中产生底切。 该第一次湿蚀刻之后是聚合干蚀刻，其通过第一次湿蚀刻产生的底切中产生聚合物膜。 聚合物膜在第二次湿法蚀刻期间防止进一步蚀刻底切部分。 因此，可以仅利用单个抗蚀剂涂敷步骤，在工件的下面部分中获得具有较大底切的底切轮廓。 工件可以是具有由相同材料形成的不同层的多层工件，或者它可以是单层材料。

公开(公告)号：US07014955B2

公开(公告)日：2006-03-21

申请号：US09941453

申请日：2001-08-28

申请人： Fang-Cheng Chang ,  Christophe Pierrat

发明人： Fang-Cheng Chang ,  Christophe Pierrat

IPC分类号： G03F9/00 ,  G06K9/00

CPC分类号： G03F1/84 ,  G03F1/36

摘要： Automated techniques for identifying dummy/main features on a mask layer are provided. In a multiple mask layer technique, the definition of a dummy/main feature can be based on connectivity information or functional association information. In a geometry technique, the definition of a dummy/main feature can be based on a feature size, a feature shape, a pattern of features, or a proximity of a feature to a neighboring feature. In one embodiment, multiple definitions and multiple techniques can be used.

公开(公告)号：US07003757B2

公开(公告)日：2006-02-21

申请号：US10855673

申请日：2004-05-26

申请人： Christophe Pierrat ,  Youping Zhang

发明人： Christophe Pierrat ,  Youping Zhang

IPC分类号： G06F17/50 ,  G03C5/00

CPC分类号： G03F1/36 ,  G03F7/70441

摘要： Techniques for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Techniques include selecting from among all edges of all polygons in a proposed layout a subset of edges for which proximity corrections are desirable. The subset of edges includes less than all the edges. Evaluation points are established only for the subset of edges. Corrections are determined for at least portions of the subset of edges based on an analysis performed at the evaluation points. Other techniques include establishing a projection point on a first edge corresponding to the design layout based on whether a vertex of a second edge is within a halo distance. An evaluation point is determined for the first edge based on the projection point and characteristics of the first edge. It is then determined how to correct at least a portion of the edge for proximity effects based on an analysis at the evaluation point.

摘要翻译： 用于制造器件的技术包括形成用于物理设计层（例如集成电路的设计）的制造布局，例如掩模布局，以及识别与设计层对应的多边形的边缘上的评估点，用于校正接近度 效果。 技术包括在所提出的布局中从所有多边形的所有边缘中选择需要接近校正的边缘子集。 边缘子集包括少于所有边缘。 仅针对边缘子集建立评估点。 基于在评估点执行的分析，确定边缘子集的至少部分的校正。 其他技术包括基于第二边缘的顶点是否在光晕距离内，在对应于设计布局的第一边缘上建立投影点。 基于投影点和第一边缘的特性，确定第一边缘的评估点。 然后基于评估点的分析确定如何校正边缘的至少一部分以用于邻近效应。

公开(公告)号：US06985847B2

公开(公告)日：2006-01-10

申请号：US10231627

申请日：2002-08-29

申请人： James Burdorf ,  Christophe Pierrat

发明人： James Burdorf ,  Christophe Pierrat

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G03F7/705 ,  G03F7/70441 ,  Y10S430/143 ,  Y10S430/168

摘要： A computer-implemented method for matching parameters of outputs generated by a first and second process. The first process generates a first output having a characteristic measurable by a first parameter, and the second process generates a second output having the characteristic measurable by a second parameter. A computer having a processing unit and memory is provided. The computer generates a first model of the first parameter for the first process and a second model of the second parameter for the second process. The computer generates a first simulated output of the first process using the first model. A correction, which is a function of the second model and which compensates for the effect of the second process on the second parameter, is applied to the first simulated output to obtain a corrected output. The second process is applied to the corrected output to generate with the computer thereby a third output matching the first parameter of the first output.

公开(公告)号：US06852471B2

公开(公告)日：2005-02-08

申请号：US09972428

申请日：2001-10-05

申请人： Christophe Pierrat ,  Michel Luc Côté

发明人： Christophe Pierrat ,  Michel Luc Côté

IPC分类号： G03F1/00 ,  G03F7/20 ,  G03F7/22 ,  H01L21/027 ,  G03B27/42 ,  G03B27/68 ,  G06F17/50

CPC分类号： G03F7/70466 ,  G03F1/26 ,  G03F1/70 ,  G03F7/70425 ,  G03F7/70433 ,  G03F7/70558

摘要： Mask and integrated circuit fabrication approaches are described to facilitate use of so called “full phase” masks. This facilitates use of masks where substantially all of a layout is defined using phase shifting. More specifically, exposure settings including relative dosing between the phase shift mask and the trim masks are described. Additionally, single reticle approaches for accommodating both masks are considered. In one embodiment, the phase shifting mask and the trim mask are exposed using the same exposure conditions, except for relative dosing. In another embodiment, the relative dosing between the phase and trim patterns is 1.0:r, 2.0

摘要翻译： 描述掩模和集成电路制造方法以便于使用所谓的“全相”掩模。 这有助于使用掩模，其中使用相移来定义基本上所有的布局。 更具体地，描述包括相移掩模和修剪蒙版之间的相对配量的曝光设置。 另外，考虑了用于容纳两个掩模的单个掩模版方法。 在一个实施例中，除了相对剂量之外，使用相同的曝光条件使相移掩模和修剪掩模曝光。 在另一个实施方案中，相位和修剪图案之间的相对剂量为1.0：r，2.0

公开(公告)号：US06811935B2

公开(公告)日：2004-11-02

申请号：US10235458

申请日：2002-09-05

申请人： Christophe Pierrat

发明人： Christophe Pierrat

IPC分类号： G03F900

CPC分类号： G03F1/26 ,  G03F1/29

摘要： Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features such as transistor gates to which such structures have been limited in the past. The method includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of sub-resolution assist features within phase shift regions and optical proximity correction features to phase shift regions. In one approach, phase shift regions are laid out so that they extend around corners in a feature, and in one or more identified corners having greater process latitude, the phase shift regions are divided and assigned opposite phases in the corner. In another approach, phase shift regions are laid out so that they do not extend through the corners, and then phase shift regions are merged in all but the identified corners. Both opaque field phase shift masks and complementary binary masks defining interconnect structures and other types of structures that are not defined using phase shifting, necessary for completion of the layout of the layer are produced.

摘要翻译： 提供了技术，用于将相移技术的使用扩展到在集成电路层中复杂布局的掩模的实现，超出了过去已经限制了这种结构的所选临界尺寸特征，例如晶体管栅极。 该方法包括识别可以对其进行相移的特征，自动映射用于实现这些特征的相移区域，解决根据给定设计规则可能发生的相位冲突，以及在相移区域内应用子分辨率辅助特征 和光学邻近校正特征到相移区域。 在一种方法中，相移区域布置成使得它们在特征中的角落周围延伸，并且在具有较大工艺纬度的一个或多个识别的角落中，相移区域被分割并在角落中分配相反的相位。 在另一种方法中，布置相移区域使得它们不延伸穿过角部，然后相移区域在除所识别的角落之外的所有角落中合并。 产生不完整的场相移掩模和定义互连结构的互补二进制掩模和不使用相移定义的其它类型的结构，这些结构对于完成层的布局是必需的。