利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

44 条记录 (耗时 0.023 秒)

    Processing for overcoming extreme topography
    42.
    发明授权
    Processing for overcoming extreme topography 有权
    克服极端地形的处理

    公开(公告)号：US07915064B2

    公开(公告)日：2011-03-29

    申请号：US12538515

    申请日：2009-08-10

    申请人： Guy A. Cohen ,  Steven A. Cordes ,  Sherif A. Goma ,  Joanna Rosner ,  Jeannine M. Trewhella

    发明人： Guy A. Cohen ,  Steven A. Cordes ,  Sherif A. Goma ,  Joanna Rosner ,  Jeannine M. Trewhella

    IPC分类号： H01L21/00 ,  H01L21/311

    CPC分类号： H01L21/31051 ,  B81C1/00611 ,  B81C2201/0119 ,  H01L21/0272 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31058 ,  H01L21/3212 ,  H01L21/76838

    摘要： A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.

    摘要翻译： 通过首先平面化半导体衬底中的空腔以便创建用于后续光刻处理的平坦表面来克服极端形貌的过程。 作为极端形貌的平面化处理的结果，可以进行随后的光刻处理，包括紧邻极端地形表面（例如，深空腔或通道）的特征沉积，并且包括在空腔内沉积特征。 在第一实施例中，用于平面化半导体衬底中的腔的方法包括施加具有高耐化学性的干膜抗蚀剂。 在第二实施例中，用于平坦化空腔的方法包括使用诸如聚合物，玻璃旋转和冶金的材料来填充空腔。

    Method of fabricating integrated coil inductors for IC devices
    43.
    发明授权
    Method of fabricating integrated coil inductors for IC devices 有权
    IC器件集成线圈电感器的制造方法

    公开(公告)号：US06720230B2

    公开(公告)日：2004-04-13

    申请号：US10238746

    申请日：2002-09-10

    申请人： Raul E. Acosta ,  Melanie L. Carasso ,  Steven A. Cordes ,  Robert A. Groves ,  Jennifer L. Lund ,  Joanna Rosner

    发明人： Raul E. Acosta ,  Melanie L. Carasso ,  Steven A. Cordes ,  Robert A. Groves ,  Jennifer L. Lund ,  Joanna Rosner

    IPC分类号： H01L2120

    CPC分类号： H01L28/10 ,  H01F17/0006 ,  H01F17/0033 ,  H01F41/041 ,  H01L27/08

    摘要： A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP. After planarization the fabrication of the remaining part of the solenoidal coil is fabricated as part of the metallization in the BEOL (i.e. as line/vias of the BEOL). To further increase the cross section of the solenoidal coil part of it may be built by electrodeposition through a mask on top of the BEOL layers.

    摘要翻译： 提供一种用于制造集成在半导体芯片中的螺线管电感器的装置。 螺线管线圈部分地嵌入到蚀刻到芯片衬底中的深阱中。 线圈的非嵌入部分被制造为BEOL金属化层的一部分。 这允许螺线管的大的横截面积的匝数，从而减少匝间电容耦合。 由于本发明的螺线管线圈具有大直径的横截面，所以线圈可以制造成具有大的电感值，并且占据芯片的小面积。 所述制造工艺包括在所有FEOL步骤完成之后蚀刻衬底中的深空腔; 用电介质衬里所述空腔，然后制造将通过掩模沉积导电材料金属而嵌入的线圈部分; 通过CMP沉积其相同的电介质和平面化。 在平坦化之后，螺线管线圈的剩余部分的制造被制造为BEOL中的金属化的一部分（即，作为BEOL的线/通路）。 为了进一步增加螺线管线圈的横截面，可以通过电沉积通过BEOL层顶部的掩模来构建。