Integrated on-chip half-wave dipole antenna structure

    公开(公告)号:US06563464B2

    公开(公告)日:2003-05-13

    申请号:US09811940

    申请日:2001-03-19

    IPC分类号: H01Q138

    摘要: A semiconductor device is presented which is composed of two adjacent semiconductor chips. Each semiconductor chip has an integrated half-wave dipole antenna structure located thereon. The semiconductor chips are oriented so that the half-wave dipole antenna segments extend away from each other, allowing the segments to be effectively mated and thus form a complete full-wave dipole antenna. The two solder bumps which form the antenna are separated by a gap of approximately 200 microns. The length of each solder bump antenna is based on the wavelength and the medium of collection. Phased array antenna arrays may also be constructed from a plurality of these semiconductor chip antennae.

    MEMS RF switch with low actuation voltage
    5.
    发明授权
    MEMS RF switch with low actuation voltage 有权
    具有低致动电压的MEMS RF开关

    公开(公告)号:US06639488B2

    公开(公告)日:2003-10-28

    申请号:US09948478

    申请日:2001-09-07

    IPC分类号: H01P110

    摘要: Disclosed is a capacitive electrostatic MEMS RF switch comprised of a lower electrode that acts as both a transmission line and as an actuation electrode. Also, there is an array of one or more fixed beams above the lower electrode that is connected to ground. The lower electrode transmits the RF signal when the top beam or beams are up and when the upper beams are actuated and bent down, the transmission line is shunted to ground ending the RF transmission. A high dielectric constant material is used in the capacitive portion of the switch to achieve a high capacitance per unit area thus reducing the required chip area and enhancing the insertion loss characteristics in the non-actuated state. A gap between beam and lower electrode of less than 1 &mgr;m is incorporated in order to minimize the electrostatic potential (pull-in voltage) required to actuate the switch.

    摘要翻译: 公开了一种电容静电MEMS RF开关,其由作为传输线和致动电极两者的下电极组成。 此外,在下电极上方有一个或多个连接到地面的固定梁的阵列。 当顶部梁或梁向上时,下部电极发射RF信号,并且当上部梁被致动并向下弯曲时,传输线被分流到结束RF传输的地面。 在开关的电容部分中使用高介电常数材料以实现每单位面积的高电容,从而在非致动状态下减少所需的芯片面积并增强插入损耗特性。 引入小于1um的光束和下电极之间的间隙以便使致动开关所需的静电电位(拉入电压)最小化。

    Diaphragm activated micro-electromechanical switch
    6.
    发明授权
    Diaphragm activated micro-electromechanical switch 有权
    隔膜激活微机电开关

    公开(公告)号:US07256670B2

    公开(公告)日:2007-08-14

    申请号:US10523310

    申请日:2002-08-26

    IPC分类号: H01H51/22

    CPC分类号: H01H59/0009

    摘要: A micro-electromechanical (MEM) RF switch provided with a deflectable membrane (60) activates a switch contact or plunger (40). The membrane incorporates interdigitated metal electrodes (70) which cause a stress gradient in the membrane when activated by way of a DC electric field. The stress gradient results in a predictable bending or displacement of the membrane (60), and is used to mechanically displace the switch contact (30). An RF gap area (25) located within the cavity (250) is totally segregated from the gaps (71) between the interdigitated metal electrodes (70). The membrane is electrostatically displaced in two opposing directions, thereby aiding to activate and deactivate the switch. The micro-electromechanical switch includes: a cavity (250); at least one conductive path (20) integral to a first surface bordering the cavity; a flexible membrane (60) parallel to the first surface bordering the cavity (250), the flexible membrane (60) having a plurality of actuating electrodes (70); and a plunger (40) attached to the flexible membrane (60) in a direction away from the actuating electrodes (70), the plunger (40) having a conductive surface that makes electric contact with the conductive paths, opening and closing the switch.

    摘要翻译: 设置有可偏转膜(60)的微机电(MEM)RF开关激活开关触点或柱塞(40)。 膜包含交叉指向的金属电极(70),其通过DC电场激活时引起膜中的应力梯度。 应力梯度导致膜(60)的可预测的弯曲或位移,并且用于机械地移动开关触点(30)。 位于空腔(250)内的RF间隙区域(25)与交叉指向的金属电极(70)之间的间隙(71)完全分离。 膜在两个相反的方向上静电位移,从而有助于启动和停用开关。 微机电开关包括:空腔(250); 至少一个导电通路(20),与所述空腔相邻的第一表面成一体; 柔性膜(60),其平行于与所述腔(250)接壤的所述第一表面,所述柔性膜(60)具有多个致动电极(70); 以及沿远离所述致动电极(70)的方向附接到所述柔性膜(60)的柱塞(40),所述柱塞(40)具有导电表面,所述导电表面与所述导电路径电接触,所述开关闭合。

    Integrated coil inductors for IC devices
    9.
    发明授权
    Integrated coil inductors for IC devices 有权
    用于IC器件的集成线圈电感器

    公开(公告)号:US06492708B2

    公开(公告)日:2002-12-10

    申请号:US09808381

    申请日:2001-03-14

    IPC分类号: H01L2900

    摘要: A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP. After planarization the fabrication of the remaining part of the solenoidal coil is fabricated as part of the metallization in the BEOL (i.e. as line/vias of the BEOL). To further increase the cross section of the solenoidal coil part of it may be built by electrodeposition through a mask on top of the BEOL layers.

    摘要翻译: 提供一种用于制造集成在半导体芯片中的螺线管电感器的装置。 螺线管线圈部分地嵌入到蚀刻到芯片衬底中的深阱中。 线圈的非嵌入部分被制造为BEOL金属化层的一部分。 这允许螺线管的大的横截面积的匝数,从而减少匝间电容耦合。 由于本发明的螺线管线圈具有大直径的横截面,所以线圈可以制造成具有大的电感值,并且占据芯片的小面积。 所述制造工艺包括在所有FEOL步骤完成之后蚀刻衬底中的深空腔; 用电介质衬里所述空腔,然后制造将通过掩模沉积导电材料金属而嵌入的线圈部分; 通过CMP沉积其相同的电介质和平面化。 在平坦化之后,螺线管线圈的剩余部分的制造被制造为BEOL中的金属化的一部分(即,作为BEOL的线/通路)。 为了进一步增加螺线管线圈的横截面,可以通过电沉积通过BEOL层顶部的掩模来构建。

    Method of fabricating integrated coil inductors for IC devices
    10.
    发明授权
    Method of fabricating integrated coil inductors for IC devices 有权
    IC器件集成线圈电感器的制造方法

    公开(公告)号:US06720230B2

    公开(公告)日:2004-04-13

    申请号:US10238746

    申请日:2002-09-10

    IPC分类号: H01L2120

    摘要: A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP. After planarization the fabrication of the remaining part of the solenoidal coil is fabricated as part of the metallization in the BEOL (i.e. as line/vias of the BEOL). To further increase the cross section of the solenoidal coil part of it may be built by electrodeposition through a mask on top of the BEOL layers.

    摘要翻译: 提供一种用于制造集成在半导体芯片中的螺线管电感器的装置。 螺线管线圈部分地嵌入到蚀刻到芯片衬底中的深阱中。 线圈的非嵌入部分被制造为BEOL金属化层的一部分。 这允许螺线管的大的横截面积的匝数,从而减少匝间电容耦合。 由于本发明的螺线管线圈具有大直径的横截面,所以线圈可以制造成具有大的电感值,并且占据芯片的小面积。 所述制造工艺包括在所有FEOL步骤完成之后蚀刻衬底中的深空腔; 用电介质衬里所述空腔,然后制造将通过掩模沉积导电材料金属而嵌入的线圈部分; 通过CMP沉积其相同的电介质和平面化。 在平坦化之后,螺线管线圈的剩余部分的制造被制造为BEOL中的金属化的一部分(即,作为BEOL的线/通路)。 为了进一步增加螺线管线圈的横截面,可以通过电沉积通过BEOL层顶部的掩模来构建。