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公开(公告)号：US07915064B2
公开(公告)日：2011-03-29
申请号：US12538515
申请日：2009-08-10
IPC分类号： H01L21/00 , H01L21/311
CPC分类号： H01L21/31051 , B81C1/00611 , B81C2201/0119 , H01L21/0272 , H01L21/0337 , H01L21/31053 , H01L21/31058 , H01L21/3212 , H01L21/76838
摘要： A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.
摘要翻译： 通过首先平面化半导体衬底中的空腔以便创建用于后续光刻处理的平坦表面来克服极端形貌的过程。 作为极端形貌的平面化处理的结果，可以进行随后的光刻处理，包括紧邻极端地形表面（例如，深空腔或通道）的特征沉积，并且包括在空腔内沉积特征。 在第一实施例中，用于平面化半导体衬底中的腔的方法包括施加具有高耐化学性的干膜抗蚀剂。 在第二实施例中，用于平坦化空腔的方法包括使用诸如聚合物，玻璃旋转和冶金的材料来填充空腔。
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公开(公告)号：US20110130005A1
公开(公告)日：2011-06-02
申请号：US13024711
申请日：2011-02-10
IPC分类号： H01L21/3105
CPC分类号： H01L21/31051 , B81C1/00611 , B81C2201/0119 , H01L21/0272 , H01L21/0337 , H01L21/31053 , H01L21/31058 , H01L21/3212 , H01L21/76838
摘要： A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.
摘要翻译： 通过首先平面化半导体衬底中的空腔以便创建用于后续光刻处理的平坦表面来克服极端形貌的过程。 作为极端形貌的平面化处理的结果，可以进行随后的光刻处理，包括紧邻极端地形表面（例如，深空腔或通道）的特征沉积，并且包括在空腔内沉积特征。 在第一实施例中，用于平面化半导体衬底中的腔的方法包括施加具有高耐化学性的干膜抗蚀剂。 在第二实施例中，用于平坦化空腔的方法包括使用诸如聚合物，玻璃旋转和冶金的材料来填充空腔。
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公开(公告)号：US20090298292A1
公开(公告)日：2009-12-03
申请号：US12538515
申请日：2009-08-10
IPC分类号： H01L21/3105
CPC分类号： H01L21/31051 , B81C1/00611 , B81C2201/0119 , H01L21/0272 , H01L21/0337 , H01L21/31053 , H01L21/31058 , H01L21/3212 , H01L21/76838
摘要： A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.
摘要翻译： 通过首先平面化半导体衬底中的空腔以便创建用于后续光刻处理的平坦表面来克服极端形貌的过程。 作为极端形貌的平面化处理的结果，可以进行随后的光刻处理，包括紧邻极端地形表面（例如，深空腔或通道）的特征沉积，并且包括在空腔内沉积特征。 在第一实施例中，用于平面化半导体衬底中的腔的方法包括施加具有高耐化学性的干膜抗蚀剂。 在第二实施例中，用于平坦化空腔的方法包括使用诸如聚合物，玻璃旋转和冶金的材料来填充空腔。
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公开(公告)号：US08603846B2
公开(公告)日：2013-12-10
申请号：US13024711
申请日：2011-02-10
IPC分类号： H01L21/00
CPC分类号： H01L21/31051 , B81C1/00611 , B81C2201/0119 , H01L21/0272 , H01L21/0337 , H01L21/31053 , H01L21/31058 , H01L21/3212 , H01L21/76838
摘要： A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.
摘要翻译： 通过首先平面化半导体衬底中的空腔以便创建用于后续光刻处理的平坦表面来克服极端形貌的过程。 作为极端形貌的平面化处理的结果，可以进行随后的光刻处理，包括紧邻极端地形表面（例如，深空腔或通道）的特征沉积，并且包括在空腔内沉积特征。 在第一实施例中，用于平面化半导体衬底中的腔的方法包括施加具有高耐化学性的干膜抗蚀剂。 在第二实施例中，用于平坦化空腔的方法包括使用诸如聚合物，玻璃旋转和冶金的材料来填充空腔。
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公开(公告)号：US06798953B1
公开(公告)日：2004-09-28
申请号：US09479109
申请日：2000-01-07
申请人： Mitchell S. Cohen , Michael J. Cordes , Steven A. Cordes , William K. Hogan , Glen W. Johnson , Daniel M. Kuchta , Dianne L. Lacey , James L. Speidell , Jeannine M. Trewhella , Joseph P. Zinter
发明人： Mitchell S. Cohen , Michael J. Cordes , Steven A. Cordes , William K. Hogan , Glen W. Johnson , Daniel M. Kuchta , Dianne L. Lacey , James L. Speidell , Jeannine M. Trewhella , Joseph P. Zinter
IPC分类号： G02B630
CPC分类号： G02B6/4246 , G02B6/3652 , G02B6/423 , G02B6/4239
摘要： A structure that includes a substrate, typically a semiconductor chip such as a VCSEL or photodetector chip, and a guide for aligning a signal conveying device, typically an optical fiber, to a transducer such as an optoelectronic device on the semiconductor chip. The guide is formed, in a preferred embodiment, by lithographically exposing and developing a thick layer of photoresist. The structure is assembled by placing and securing the signal conveying device into a cavity-like region of the guide.
摘要翻译： 包括基板，通常为诸如VCSEL或光电检测器芯片的半导体芯片的结构，以及用于将信号传送装置（通常为光纤）对准到诸如半导体芯片上的光电子装置的换能器的引导件。 在优选实施例中，通过光刻曝光和显影厚的光致抗蚀剂层来形成引导件。 通过将信号传送装置放置并固定到引导件的腔状区域来组装结构。
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6.发明授权Interconnecting (mapping) a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array 有权将二维光电（OE）器件阵列互连（映射）到一维波导阵列公开(公告)号：US07883277B2
公开(公告)日：2011-02-08
申请号：US12117803
申请日：2008-05-09
申请人： Russell A. Budd , Punit P. Chiniwalla , John A. Guckenberger , Jeffrey A. Kash , Jeremy D. Schaub , Michael Tan , Jeannine M. Trewhella , Garry Trott
发明人： Russell A. Budd , Punit P. Chiniwalla , John A. Guckenberger , Jeffrey A. Kash , Jeremy D. Schaub , Michael Tan , Jeannine M. Trewhella , Garry Trott
CPC分类号： G02B6/43 , G02B6/42 , G02B6/4214 , G02B6/4246
摘要： For integrated circuits including circuit packaging and circuit communication technologies provision is made for a method of interconnecting or mapping a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array. Also provided is an arrangement for the interconnecting or mapping of a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array.
摘要翻译： 对于包括电路封装和电路通信技术的集成电路，提供了将二维光电（OE）器件阵列互连或映射到一维波导阵列的方法。 还提供了用于将二维光电（OE）器件阵列互连或映射到一维波导阵列的布置。
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公开(公告)号：US06940165B2
公开(公告)日：2005-09-06
申请号：US10241403
申请日：2002-09-11
IPC分类号： H01L23/495 , H01L23/64 , H01L23/48
CPC分类号： H01L23/4952 , H01L23/645 , H01L24/48 , H01L24/49 , H01L2223/6627 , H01L2224/05599 , H01L2224/45099 , H01L2224/49171 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/1903 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： An improved electrical interconnect is formed wherein a dielectric material having a controllable characteristic is applied to at least a portion of the interconnect. The controllable characteristic of the dielectric material is selectively adjustable so that the impedance of the electrical interconnect is substantially matched to at least one impedance at first and second ends of the interconnect. In this manner, an electrical discontinuity between the first and second ends of the electrical interconnect is reduced, thereby improving an electrical performance of the interconnect.
摘要翻译： 形成改进的电互连，其中具有可控特性的介电材料被施加到互连的至少一部分。 电介质材料的可控特性可选择性地调节，使得电互连的阻抗基本上与互连的第一和第二端处的至少一个阻抗匹配。 以这种方式，电互连的第一和第二端之间的电中断减小，从而提高互连的电性能。
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8.发明授权
公开(公告)号：US5495545A
公开(公告)日：1996-02-27
申请号：US328177
申请日：1994-10-24
申请人： Michael F. Cina , Dennis L. Karst , Modest M. Oprysko , Mark B. Ritter , Stephen L. Spanoudis , Jeannine M. Trewhella
发明人： Michael F. Cina , Dennis L. Karst , Modest M. Oprysko , Mark B. Ritter , Stephen L. Spanoudis , Jeannine M. Trewhella
CPC分类号： G02B6/4206
摘要： A method for making an optical fiber transmission apparatus for limiting the optical modes which were emitted from a source in such a way to impinge on an optical fiber to extract a high bandwidth from the fiber. The apparatus includes a lens or aperture to control the angle and distribution of light launched into the fiber. The apparatus achieves reproducibly high bandwidths in large core step-index optical fibers of short transmission length distances. The lens or aperture introduces light from the source into the fiber at an angle at which substantially no intermode delay occurs as the light propagates down the fiber. An integral fiber optic coupling assembly that includes an optical electronic component receptacle, the lens and/or aperture, and an optical fiber connector interface which provides low cost easy to manufacture assembly is also disclosed. A unitary plastic housing provides the function of a lens and mechanical reference or locating features for the light source and optical fiber.
摘要翻译： 一种制造光纤传输装置的方法，用于限制从源发射的光模，以照射到光纤上以从光纤提取高带宽。 该装置包括用于控制发射到光纤中的光的角度和分布的透镜或孔。 该装置在具有短传输长度距离的大型核心阶跃折射率光纤中实现可重复的高带宽。 透镜或光圈将光从光源引入光纤，其角度基本上不发生模式间延迟，因为光沿着光纤传播。 还公开了一种包括光学电子部件插座，透镜和/或孔径以及提供低成本易于制造组装的光纤连接器接口的整体光纤耦合组件。 单一的塑料外壳提供了一个透镜的功能，并为光源和光纤提供机械参考或定位功能。
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9.发明申请INTERCONNECTING (MAPPING) A TWO-DIMENSIONAL OPTOELECTRONIC (OE) DEVICE ARRAY TO A ONE-DIMENSIONAL WAVEGUIDE ARRAY 有权互连（映射）二维光电（OE）器件阵列到一维波形阵列公开(公告)号：US20080205817A1
公开(公告)日：2008-08-28
申请号：US12117803
申请日：2008-05-09
申请人： Russell A. Budd , Punit P. Chiniwalla , John A. Guckenberger , Jeffrey A. Kash , Jeremy D. Schaub , Michael Tan , Jeannine M. Trewhella , Garry Trott
发明人： Russell A. Budd , Punit P. Chiniwalla , John A. Guckenberger , Jeffrey A. Kash , Jeremy D. Schaub , Michael Tan , Jeannine M. Trewhella , Garry Trott
CPC分类号： G02B6/43 , G02B6/42 , G02B6/4214 , G02B6/4246
摘要： For integrated circuits including circuit packaging and circuit communication technologies provision is made for a method of interconnecting or mapping a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array. Also provided is an arrangement for the interconnecting or mapping of a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array.
摘要翻译： 对于包括电路封装和电路通信技术的集成电路，提供了将二维光电（OE）器件阵列互连或映射到一维波导阵列的方法。 还提供了用于将二维光电（OE）器件阵列互连或映射到一维波导阵列的布置。
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公开(公告)号：US07308167B2
公开(公告)日：2007-12-11
申请号：US10931713
申请日：2004-09-01
CPC分类号： G02B6/423 , G02B6/4214 , G02B6/4228 , G02B6/4232
摘要： At least one optical waveguide is supported on a substrate and has a plurality of key apertures formed in a complaint element thereof. An optoelectronic device such as a vertical cavity surface emitting laser (VCSEL) has a plurality of projections that register with corresponding key apertures to position the optoelectronic device in a predetermined alignment relative to the optical waveguide.
摘要翻译： 至少一个光波导支撑在基板上，并且在其投诉元件中形成有多个键孔。 诸如垂直腔表面发射激光器（VCSEL）的光电子器件具有多个突起，其与相应的键孔对准，以相对于光波导以预定的对准定位光电器件。
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