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    Integrated circuit having angled conductive feature
    41.
    发明授权
    Integrated circuit having angled conductive feature 有权

    公开(公告)号：US11631661B2

    公开(公告)日：2023-04-18

    申请号：US17317216

    申请日：2021-05-11

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Tung-Heng Hsieh ,  Ting-Wei Chiang ,  Chung-Te Lin ,  Hui-Zhong Zhuang ,  Li-Chun Tien ,  Sheng-Hsiung Wang

    IPC: H01L27/02 ,  G06F30/39 ,  G06F30/392 ,  G06F30/398 ,  H01L23/528 ,  H01L27/092

    Abstract: An integrated circuit includes a first gate electrode structure extending in a first direction and having a first portion and a second portion separated from each other. The integrated circuit further includes a second gate electrode structure extending in the first direction and separated in a second direction from the first gate electrode structure. The integrated circuit further includes a conductive feature. The conductive feature includes a first section electrically connected to the second portion, wherein the first section extends in the second direction. The conductive feature further includes a second section electrically connected to the second gate electrode structure, wherein the second section extends in the second direction. The conductive feature further includes a third section electrically connecting the first section and the second section, wherein the third section extends in a third direction angled with respect to both the first direction and the second direction.

    Clock gating circuit and method of operating the same
    42.
    发明授权
    Clock gating circuit and method of operating the same 有权

    公开(公告)号：US11545965B2

    公开(公告)日：2023-01-03

    申请号：US17095191

    申请日：2020-11-11

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Seid Hadi Rasouli ,  Jerry Chang Jui Kao ,  Xiangdong Chen ,  Tzu-Ying Lin ,  Yung-Chen Chen ,  Hui-Zhong Zhuang ,  Chi-Lin Liu

    IPC: H03K3/037 ,  G06F1/12 ,  H03K19/20

    Abstract: A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.

    SEMICONDUCTOR DEVICE INCLUDING RECESSED INTERCONNECT STRUCTURE
    46.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING RECESSED INTERCONNECT STRUCTURE 有权

    公开(公告)号：US20220302027A1

    公开(公告)日：2022-09-22

    申请号：US17836896

    申请日：2022-06-09

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Guo-Huei Wu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Cheng-Chi Chuang ,  Shang-Wen Chang ,  Yi-Hsun Chiu

    IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

    Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.

    Integrated circuit and method of manufacturing same
    47.
    发明授权
    Integrated circuit and method of manufacturing same 有权

    公开(公告)号：US11409938B2

    公开(公告)日：2022-08-09

    申请号：US17140368

    申请日：2021-01-04

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Li-Chun Tien

    IPC: G06F30/392 ,  H01L27/02 ,  H01L27/092

    Abstract: An integrated circuit includes a first and a second set of conductive traces. The first set of conductive traces is in a first level and extends in a first direction. The second set of conductive traces is in a second level and extends in a second direction. The second set of conductive traces includes a first conductive trace corresponding to a gate terminal of a first p-type transistor and a gate terminal of a first n-type transistor, and a second conductive trace corresponding to a gate terminal of a second n-type transistor and a gate terminal of a second p-type transistor. The first and second conductive trace are separated from each other in the first direction. The first n-type transistor and the second p-type transistor are part of a first transmission gate. The second n-type transistor and the first p-type transistor are part of a second transmission gate.

    Reduced area standard cell abutment configurations
    49.
    发明授权
    Reduced area standard cell abutment configurations 有权

    公开(公告)号：US11216608B2

    公开(公告)日：2022-01-04

    申请号：US16664242

    申请日：2019-10-25

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    Inventor： Chi-Yu Lu ,  Hui-Zhong Zhuang ,  Li-Chun Tien ,  Pin-Dai Sue ,  Yi-Hsin Ko

    IPC: G06F30/392 ,  G06F30/398

    Abstract: A semiconductor device comprising at least one modified cell block that includes a modified abutment region in which is provided a first continuous active region arranged along a first axis parallel to a vertical abutment edge for positioning adjacent other cell blocks to form a vertical abutment, including non-standard, standard, and modified cell blocks. The structure provided within the modified abutment region improves a structural and device density match between the modified cell block and the adjacent cell block, thereby reducing the need for white space between vertically adjacent cell blocks and reducing the total device area and increasing cell density.

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