公开(公告)号：US09088271B2

公开(公告)日：2015-07-21

申请号：US14035250

申请日：2013-09-24

Applicant: Texas Instruments Incorporated

Inventor： Steven Bartling ,  Sudhanshu Khanna

IPC: H03K3/356 ,  H03K3/037

CPC classification number: H03K3/0375

Abstract: In an embodiment of the invention, a dual-port positive level sensitive data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal (CKT) goes high, (CLKZ) goes low and retention control signal is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit (D2), the clock signals (CKT) and (CLKN), the retain control signals (RET) and the control signals SS (SS) and (SSN). The signals (CKT), (CLKZ), (RET), (SS) and (SSN) determine whether the output of the clocked inverter or the second data bit (D2) is latched in the dual-port latch. Control signal (RET) determines when data is stored in the dual-port latch during retention mode.

Abstract translation: 在本发明的一个实施例中，双端口正电平敏感数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号（CKT）变高，（CLKZ）变为低电平，保持控制信号为低电平时，数据通过时钟反相器进行时钟输入。 双端口锁存器被配置为接收时钟反相器的输出，第二数据位（D2），时钟信号（CKT）和（CLKN），保持控制信号（RET）和控制信号SS（SS） 和（SSN）。 信号（CKT），（CLKZ），（RET），（SS）和（SSN）确定时钟反相器或第二数据位（D2）的输出是否锁存在双端口锁存器中。 在保留模式期间，控制信号（RET）确定数据何时存储在双端口锁存器中。

公开(公告)号：US09013217B2

公开(公告)日：2015-04-21

申请号：US14311752

申请日：2014-06-23

Applicant: Texas Instruments Incorporated

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: H03K3/00 ,  H03K3/356

CPC classification number: H03K3/356008

Abstract: In an embodiment of the invention, a dual-port negative level sensitive data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and the control signals SS and SSN. The signals CKT, CLKZ, RET, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.

Abstract translation: 在本发明的一个实施例中，双端口负电平敏感数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号CKT变高，CLKZ变为低电平，保持控制信号RET为低电平时，数据通过时钟反相器进行时钟输入。 双端口锁存器被配置为接收时钟反相器的输出，第二数据位D2，时钟信号CKT和CLN，保持控制信号RET和控制信号SS和SSN。 信号CKT，CLKZ，RET，SS和SSN确定时钟反相器或第二数据位D2的输出是否锁存在双端口锁存器中。 在保持模式期间，控制信号RET确定数据何时存储在双端口锁存器中。

公开(公告)号：US09007091B2

公开(公告)日：2015-04-14

申请号：US14080092

申请日：2013-11-14

Applicant: Texas Instruments Incorporated

Inventor： Steven C. Bartling ,  Sudhanshu Khanna

IPC: H03K19/173

CPC classification number: H03K19/1735 ,  H03K3/356008

Abstract: In an embodiment of the invention, a dual-port positive level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.

Abstract translation: 在本发明的实施例中，双端口正电平敏感预设数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号CKT变高，CLKZ变为低电平，预置控制信号PRE为低电平，保持控制信号RET为低电平时，数据由时钟反相器提供时钟。 双端口锁存器被配置为接收时钟反相器的输出，第二数据位D2，时钟信号CKT和CLKZ，保持控制信号RET和RETN，预置控制信号PRE和控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，PRE，SS和SSN确定时钟反相器或第二数据位D2的输出是否锁存在双端口锁存器中。 在保留模式期间，控制信号RET和RETN确定数据是否存储在双端口锁存器中。

公开(公告)号：US20150042390A1

公开(公告)日：2015-02-12

申请号：US14035250

申请日：2013-09-24

Applicant: Texas Instruments Incorporated

Inventor： Steven Bartling ,  Sudhanshu Khanna

IPC: H03K3/037

CPC classification number: H03K3/0375

Abstract: In an embodiment of the invention, a dual-port positive level sensitive data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and the control signals SS and SSN. The signals CKT, CLKZ, RET, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.

Abstract translation: 在本发明的一个实施例中，双端口正电平敏感数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号CKT变高，CLKZ变为低电平，保持控制信号RET为低电平时，数据通过时钟反相器进行时钟输入。 双端口锁存器被配置为接收时钟反相器的输出，第二数据位D2，时钟信号CKT和CLN，保持控制信号RET和控制信号SS和SSN。 信号CKT，CLKZ，RET，SS和SSN确定时钟反相器或第二数据位D2的输出是否锁存在双端口锁存器中。 在保持模式期间，控制信号RET确定数据何时存储在双端口锁存器中。

公开(公告)号：US08897088B2

公开(公告)日：2014-11-25

申请号：US13753771

申请日：2013-01-30

Applicant: Texas Instruments Incorporated

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G11C29/50 ,  G11C29/08 ,  G11C29/34 ,  G11C11/401 ,  G11C29/02

CPC classification number: G11C29/08 ,  G11C11/22 ,  G11C11/401 ,  G11C14/0072 ,  G11C29/02 ,  G11C29/12 ,  G11C29/34 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/0401

Abstract: A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines. An AND gate is coupled to the m bit lines and has an output line coupled to an input of a test controller on the SoC. An OR gate is coupled to the m bit lines and has an output line coupled to an input of the test controller.

Abstract translation: 片上系统（SoC）提供非易失性存储器阵列，其配置为n行x位的位单元。 每个位单元被配置为存储一位数据。 存在m个位线，每个位线耦合到位单元的m列的相应一个。 存在m个写入驱动器，每个写入驱动器耦合到m个位线中的相应一个位线。 与门耦合到m位线，并且具有耦合到SoC上的测试控制器的输入的输出线。 OR门耦合到m位线，并且具有耦合到测试控制器的输入的输出线。

公开(公告)号：US08836399B2

公开(公告)日：2014-09-16

申请号：US13759249

申请日：2013-02-05

Applicant: Texas Instruments Incorporated

Inventor： Steven Bartling ,  Sudhanshu Khanna

IPC: H03K3/289 ,  H03K3/012

CPC classification number: H03K3/3562 ,  G01R31/318541 ,  H03K3/012 ,  H03K3/35625

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract translation: 在本发明的实施例中，触发器电路包含2输入多路复用器，主锁存器，传输门和从锁存器。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CLK和CLKN以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CLK和CLN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CLK，CLKN，RET，RETN，SS和SSN确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。

公开(公告)号：US20140232439A1

公开(公告)日：2014-08-21

申请号：US14154586

申请日：2014-01-14

Applicant: Texas Instruments Incorporated

Inventor： Steven Bartling ,  Sudhanshu Khanna

IPC: H03K3/3562

CPC classification number: H03K3/35625

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLKN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN RE, and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract translation: 在本发明的实施例中，触发器电路包含2输入多路复用器，主锁存器，传输门和从锁存器。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CKT和CLKZ以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CKT和CLKN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，SS，SSN RE和PREN确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。

公开(公告)号：US20140218091A1

公开(公告)日：2014-08-07

申请号：US13759249

申请日：2013-02-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Bartling ,  Sudhanshu Khanna

IPC: H03K3/012

CPC classification number: H03K3/3562 ,  G01R31/318541 ,  H03K3/012 ,  H03K3/35625

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract translation: 在本发明的实施例中，触发器电路包含2输入多路复用器，主锁存器，传输门和从锁存器。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CLK和CLKN以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CLK和CLN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CLK，CLKN，RET，RETN，SS和SSN确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。

公开(公告)号：US20140211532A1

公开(公告)日：2014-07-31

申请号：US13753782

申请日：2013-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G11C11/22

CPC classification number: G11C11/221

Abstract: A system on chip (SoC) provides a memory array of nonvolatile bitcells. Each bit cell includes two ferroelectric capacitors connected in series between a first plate line and a second plate line, such that a node Q is formed between the two ferroelectric capacitors. The first plate line and the second plate line are configured to provide a voltage approximately equal to first voltage while the bit cell is not being accessed. A clamping circuit is coupled to the node Q and is operable to clamp the node Q to a voltage approximately equal to first voltage while the bit cell is not being accessed.

Abstract translation: 片上系统（SoC）提供了非易失性位单元的存储器阵列。 每个位单元包括在第一板线和第二板线之间串联连接的两个铁电电容器，使得在两个铁电电容器之间形成节点Q。 第一板线和第二板线配置成在位单元未被访问时提供大致等于第一电压的电压。 钳位电路耦合到节点Q并且可操作以在不访问位单元的情况下将节点Q钳位到大致等于第一电压的电压。

公开(公告)号：US20140075174A1

公开(公告)日：2014-03-13

申请号：US13770041

申请日：2013-02-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F9/44

CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

Abstract: A processing device using a plurality of volatile storage elements to execute a boot process for and stores in a plurality of non-volatile logic element arrays a boot state representing a state of the processing device after a given amount of the boot process is completed. When it is determined that the processing device needs to restart from a boot state, energy can be saved by restoring the machine state at that boot state instead of re-booting. The stored boot state will not change, and given the nature of certain non-volatile storage elements, the data read from the NVL storage elements needs to be re-written to the elements after read out. Accordingly, a round-trip data restoration operation is executed that automatically writes back data to an individual non-volatile logic element after reading data from the individual non-volatile logic element without completing separate read and write operations.

Abstract translation: 一种处理装置，其使用多个易失性存储元件来执行引导处理并且在多个非易失性逻辑元件阵列中存储表示在给定量的引导处理之后处理装置的状态的引导状态。 当确定处理设备需要从引导状态重新启动时，可以通过在引导状态下恢复机器状态而不是重新引导来节省能量。 存储的启动状态不会改变，并且鉴于某些非易失性存储元件的性质，从NVL存储元件读取的数据需要在读出后重新写入元件。 因此，执行往返数据恢复操作，其在从单独的非易失性逻辑元件读取数据之后自动将数据写回单个非易失性逻辑元件，而不完成单独的读取和写入操作。