Galvanic isolator
    42.
    发明授权
    Galvanic isolator 有权
    电隔离器

    公开(公告)号:US09496926B2

    公开(公告)日:2016-11-15

    申请号:US14050984

    申请日:2013-10-10

    CPC classification number: H02J50/12 H02J50/23 H04B5/005 H04B5/0087

    Abstract: A system on a package (SOP) can include a galvanic isolator. The galvanic isolator can include an input stage configured to transmit an input RF signal in response to receiving an input modulated signal. The galvanic isolator can also include a resonant coupler electrically isolated from the input stage by a dielectric. The resonant coupler can be configured to filter the input RF signal and transmit an output RF signal in response to the input RF signal. The galvanic isolator can further include an output stage electrically isolated from the resonant coupler by the dielectric. The output stage can be configured to provide an output modulated signal in response to receiving the output RF signal.

    Abstract translation: 封装上的系统(SOP)可以包括电隔离器。 电流隔离器可以包括输入级,其被配置为响应于接收到输入调制信号而发送输入RF信号。 电流隔离器还可以包括通过电介质与输入级电隔离的谐振耦合器。 谐振耦合器可以被配置为对输入的RF信号进行滤波,并响应输入的RF信号传输输出的RF信号。 电流隔离器还可以包括通过电介质与谐振耦合器电隔离的输出级。 输出级可以被配置为响应于接收输出RF信号而提供输出调制信号。

    Systems and methods of polyphase generation
    43.
    发明授权
    Systems and methods of polyphase generation 有权
    多相生成的系统和方法

    公开(公告)号:US09438456B1

    公开(公告)日:2016-09-06

    申请号:US14887566

    申请日:2015-10-20

    Abstract: Example embodiments of the systems and methods of polyphase generation involve quadrature generation in high frequency digital transceivers. An oscillation signal is received and converted to complex variables with lead and lag phase rotation while performing compensation and calibration due to non-idealities of the in-phase and quadrature phase component parts. In addition to orthagonalizating, the quadrature generator also provides signal amplification and filtering. The quadrature phase generation scheme may be extended to odd harmonics of the fundamental frequency at the input.

    Abstract translation: 多相生成的系统和方法的示例实施例涉及高频数字收发器中的正交生成。 由于同相和正交相位分量的非理想性,在进行补偿和校准的同时,接收振荡信号并将其转换为带有前导和滞后相位旋转的复数变量。 除了对角化之外,正交发生器还提供信号放大和滤波。 正交相位生成方案可以扩展到输入端的基频的奇次谐波。

    Isolation circuits for digital communications and methods to provide isolation for digital communications
    44.
    发明授权
    Isolation circuits for digital communications and methods to provide isolation for digital communications 有权
    用于数字通信的隔离电路和为数字通信提供隔离的方法

    公开(公告)号:US09379746B2

    公开(公告)日:2016-06-28

    申请号:US14732313

    申请日:2015-06-05

    Abstract: Isolation circuits for digital communications and methods to provide isolation for digital communications are disclosed. An example isolation circuit includes an isolation barrier, a burst encoder in a first circuit, and an edge pattern detector in a second circuit. The example isolation barrier electrically isolates the first circuit from the second circuit. The example burst encoder generates a first pattern in response to receiving a rising edge on an input signal and generates a second pattern in response to receiving a falling edge on the input signal. The example edge pattern detector detects the first pattern or the second pattern received from the burst encoder via the isolation barrier, sets an output signal at a first signal level in response to detecting the first pattern, and sets the output signal at a second signal level in response to detecting the second pattern.

    Abstract translation: 公开了用于数字通信的隔离电路和用于提供用于数字通信的隔离的方法。 示例性隔离电路包括隔离栅,第一电路中的突发编码器和第二电路中的边缘图案检测器。 示例性隔离屏障将第一电路与第二电路电隔离。 响应于在输入信号上接收上升沿,示例性突发编码器产生第一模式,并且响应于在输入信号上接收到下降沿而产生第二模式。 示例性边缘模式检测器经由隔离屏障检测从脉冲串编码器接收的第一模式或第二模式,响应于检测到第一模式而将输出信号设置在第一信号电平,并将输出信号设置在第二信号电平 响应于检测到第二图案。

    Method and circuitry for transmitting data
    45.
    发明授权
    Method and circuitry for transmitting data 有权
    用于传输数据的方法和电路

    公开(公告)号:US09209842B2

    公开(公告)日:2015-12-08

    申请号:US14290610

    申请日:2014-05-29

    CPC classification number: H04B1/0475 H04B1/0483 H04M11/066

    Abstract: Data transfer devices and methods for transferring data between first and second circuits are disclosed. A data transfer device includes a first circuit having a plurality of data channels, wherein at least one of the data channels is an active data channel. A serializer has a plurality of inputs and an output, wherein the inputs are coupled to the plurality of data channels. The serializer is for coupling only one active channel at a time to the output. An isolation barrier is coupled to the output of the serializer, the isolation attenuates transients and passes the fundamental frequency. A second circuit includes a deserializer having an input and at least one output, the input is coupled to the isolation barrier, the at least one output is at least one active data channel.

    Abstract translation: 公开了用于在第一和第二电路之间传送数据的数据传送装置和方法。 数据传输装置包括具有多个数据信道的第一电路,其中至少一个数据信道是活动数据信道。 串行器具有多个输入和输出,其中输入耦合到多个数据信道。 串行器仅用于将一个活动通道一次耦合到输出。 隔离栅耦合到串行器的输出端,隔离衰减瞬变并通过基频。 第二电路包括具有输入和至少一个输出的解串器,该输入耦合到隔离屏障,该至少一个输出是至少一个有效数据通道。

    ON-CHIP DIRECTIONAL COUPLER
    46.
    发明申请

    公开(公告)号:US20250096450A1

    公开(公告)日:2025-03-20

    申请号:US18966557

    申请日:2024-12-03

    Abstract: An on-chip directional coupler includes a first linear conductive trace, a second linear conductive trace, and a conductive loop. The first linear conductive trace including an end and a coupled port. The second linear conductive trace is spaced apart from and parallel to the first linear conductive trace. The second linear conductive trace includes an end and an isolated port. The conductive loop includes a first end conductively coupled to the end of the first linear conductive trace, and a second end conductively coupled to the end of the second linear conductive trace.

    Broadband Frequency Multiplier with Harmonic Suppression

    公开(公告)号:US20240223168A1

    公开(公告)日:2024-07-04

    申请号:US18148845

    申请日:2022-12-30

    CPC classification number: H03K5/00006 G06F1/08 H03H7/0115 H03H7/0161

    Abstract: Described embodiments include a circuit having a quadrature phase generator circuit having differential generator inputs, in-phase differential generator outputs and quadrature-phase differential generator outputs. A first frequency multiplier circuit has first differential multiplier inputs and a first multiplier output, wherein the first differential multiplier inputs are coupled to the in-phase differential generator outputs. A second frequency multiplier circuit has second differential multiplier inputs and a second multiplier output. The second multiplier differential inputs are coupled to the quadrature-phase differential generator outputs. A transformer includes a primary inductor and a secondary inductor, wherein the primary inductor is coupled between the first and second multiplier outputs, and the second inductor is coupled between an output voltage terminal and a ground terminal.

    MULTI-TERMINAL SWITCH
    48.
    发明公开

    公开(公告)号:US20240178877A1

    公开(公告)日:2024-05-30

    申请号:US18072667

    申请日:2022-11-30

    CPC classification number: H04B1/44 H03K17/6871

    Abstract: In described examples, a multi-terminal switch includes first and second switches, and first, second, and third inductors. The first switch and first inductor are coupled between first terminals, the second switch and second inductor are coupled between second terminals, and the third inductor is coupled between third terminals. In a first mode, the first switch is opened and the second switch is closed. Opening the first switch and closing the second switch enables a first connection between the first terminals and the third terminals via a first magnetic coupling between the first and third inductors. In a second mode, the first switch is closed and the second switch is opened. Closing the first switch and opening the second switch enables a second connection between the second terminals and the third terminals via a second magnetic coupling between the second and third inductors.

    Single stage frequency multiplier using different types of signal mixing modes

    公开(公告)号:US11652446B2

    公开(公告)日:2023-05-16

    申请号:US17694953

    申请日:2022-03-15

    CPC classification number: H03D7/1458 H03D7/125 H03D7/1433 H03D7/1441 H03D7/16

    Abstract: A frequency multiplier includes an input section having inputs to receive an input signal having an input frequency, a mixer section, and an output section magnetically coupled to the input section and generating an output signal in response to the input signal. The mixer section may be coupled to the input section by a common mode node forming a path for a common mode current to flow to the mixer section and be magnetically coupled to the common mode node. The input section may generate a signal current, and the mixer section may be magnetically coupled to the input section and be directly capacitively coupled to the input section through a capacitor in a signal current path. The mixer section may have differential inputs capacitively coupled to the input section and also be coupled to the input section through a current path. A current helper section may be coupled to the current path.

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