公开(公告)号：US20230207634A1

公开(公告)日：2023-06-29

申请号：US18178893

申请日：2023-03-06

Applicant: Taiwan Semiconductor Manufacturing co., Ltd.

Inventor： Shahaji B. More ,  Cheng-Han Lee ,  Shih-Chieh Chang ,  Shih-Ya Lin ,  Chung-En Tsai ,  Chee-Wee Liu

IPC: H01L29/161 ,  H01L29/786 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/161 ,  H01L29/78696 ,  H01L29/401 ,  H01L29/66742 ,  H01L29/42392

Abstract: The present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. The buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. The semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. The epitaxial structure includes germanium and tin.

公开(公告)号：US11600703B2

公开(公告)日：2023-03-07

申请号：US17162896

申请日：2021-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Cheng-Han Lee ,  Shih-Chieh Chang ,  Shih-Ya Lin ,  Chung-En Tsai ,  Chee-Wee Liu

IPC: H01L29/161 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40

Abstract: The present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. The buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. The semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. The epitaxial structure includes germanium and tin.

公开(公告)号：US20220359730A1

公开(公告)日：2022-11-10

申请号：US17815443

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chieh Chang ,  Shahaji B. More ,  Cheng-Han Lee

IPC: H01L29/66 ,  H01L29/267 ,  H01L29/08 ,  H01L29/78 ,  H01L29/04 ,  H01L29/165

Abstract: A method includes forming a first fin and a second fin over a substrate, depositing an isolation material surrounding the first and second fins, forming a gate structure along sidewalls and over upper surfaces of the first and second fins, recessing the first and second fins outside of the gate structure to form a first recess in the first fin and a second recess in the second fin, epitaxially growing a first source/drain material protruding from the first and second recesses, and epitaxially growing a second source/drain material on the first source/drain material, wherein the second source/drain material grows at a slower rate on outermost surfaces of opposite ends of the first source/drain material than on surfaces of the first source/drain material between the opposite ends of the first source/drain material, and wherein the second source/drain material has a higher doping concentration than the first source/drain material.

公开(公告)号：US11367784B2

公开(公告)日：2022-06-21

申请号：US16902170

申请日：2020-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shahaji B. More ,  Chien Lin ,  Cheng-Han Lee ,  Shih-Chieh Chang ,  Shu Kuan

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/161 ,  H01L29/10

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. At least one of the first semiconductor layers has a composition which changes along a stacked direction of the first semiconductor layers and second semiconductor layers.

公开(公告)号：US20220028991A1

公开(公告)日：2022-01-27

申请号：US16935890

申请日：2020-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Cheng-Han Lee

IPC: H01L29/417 ,  H01L29/04 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, and a source/drain (S/D) region adjacent to the gate structure. The S/D region can include first and second side surfaces separated from each other. The S/D region can further include top and bottom surfaces between the first and second side surfaces. A first separation between the top and bottom surfaces can be greater than a second separation between the first and second side surfaces.

公开(公告)号：US20210175359A1

公开(公告)日：2021-06-10

申请号：US17181234

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Huai-Tei Yang ,  Shih-Chieh Chang ,  Shu Kuan ,  Cheng-Han Lee

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66 ,  H01L29/161 ,  H01L21/8234

Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.

公开(公告)号：US10680106B2

公开(公告)日：2020-06-09

申请号：US15997130

申请日：2018-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Huai-Tei Yang ,  Shih-Chieh Chang ,  Cheng-Han Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/167 ,  H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L29/165 ,  H01L29/161

Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.

公开(公告)号：US10510889B2

公开(公告)日：2019-12-17

申请号：US15922681

申请日：2018-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Huai-Tei Yang ,  Shih-Chieh Chang ,  Shu Kuan ,  Cheng-Han Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L21/8234

Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.

公开(公告)号：US10026840B2

公开(公告)日：2018-07-17

申请号：US15292428

申请日：2016-10-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Zheng-Yang Pan ,  Chun-Chieh Wang ,  Cheng-Han Lee ,  Shih-Chieh Chang

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/267 ,  H01L29/36 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/8234

Abstract: Structures of a semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, and a first recess and a second recess in the substrate and at opposite sides of the gate structure. The semiconductor device also includes two source/drain structures over the first recess and the second recess respectively. At least one of the source/drain structures includes a first doped region partially filling in the first recess, a second doped region over the first doped region, and a third doped region over the second doped region. The second doped region contains more dopants than the first doped region or the third doped region.