公开(公告)号：US12249604B2

公开(公告)日：2025-03-11

申请号：US18360416

申请日：2023-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Chih-Hsiung Huang ,  Chung-En Tsai ,  Chee-Wee Liu ,  Kun-Wa Kuok ,  Yi-Hsiu Hsiao

IPC: H01L29/40 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.

公开(公告)号：US11776998B2

公开(公告)日：2023-10-03

申请号：US17582731

申请日：2022-01-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Chung-En Tsai ,  Chia-Che Chung ,  Chee-Wee Liu ,  Fang-Liang Lu ,  Yu-Shiang Huang ,  Hung-Yu Yeh ,  Chien-Te Tu ,  Yi-Chun Liu

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/0262 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02609 ,  H01L21/30604 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78696

Abstract: A device comprises a plurality of nanosheets, source/drain stressors, and a gate structure wrapping around the nanosheets. The nanosheets extend in a first direction above a semiconductor substrate and are arranged in a second direction substantially perpendicular to the first direction. The source/drain stressors are on either side of the nanosheets. Each of the source/drain stressors comprises a first epitaxial layer and a second epitaxial layer over the first epitaxial layer. The first and second epitaxial layers are made of a Group IV element and a Group V element. An atomic ratio of the Group V element to the Group IV element in the second epitaxial layer is greater than an atomic ratio of the Group V element to the Group IV element in the first epitaxial layer.

公开(公告)号：US20230207634A1

公开(公告)日：2023-06-29

申请号：US18178893

申请日：2023-03-06

Applicant: Taiwan Semiconductor Manufacturing co., Ltd.

Inventor： Shahaji B. More ,  Cheng-Han Lee ,  Shih-Chieh Chang ,  Shih-Ya Lin ,  Chung-En Tsai ,  Chee-Wee Liu

IPC: H01L29/161 ,  H01L29/786 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/161 ,  H01L29/78696 ,  H01L29/401 ,  H01L29/66742 ,  H01L29/42392

Abstract: The present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. The buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. The semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. The epitaxial structure includes germanium and tin.

公开(公告)号：US11600703B2

公开(公告)日：2023-03-07

申请号：US17162896

申请日：2021-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Cheng-Han Lee ,  Shih-Chieh Chang ,  Shih-Ya Lin ,  Chung-En Tsai ,  Chee-Wee Liu

IPC: H01L29/161 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40

Abstract: The present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. The buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. The semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. The epitaxial structure includes germanium and tin.

公开(公告)号：US11791338B2

公开(公告)日：2023-10-17

申请号：US17585020

申请日：2022-01-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Chih-Hsiung Huang ,  Chung-En Tsai ,  Chee-Wee Liu ,  Kun-Wa Kuok ,  Yi-Hsiu Hsiao

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/40

CPC classification number: H01L27/092 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.

公开(公告)号：US10777663B2

公开(公告)日：2020-09-15

申请号：US16150182

申请日：2018-10-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Chung-En Tsai ,  Fang-Liang Lu ,  Pin-Shiang Chen ,  Chee-Wee Liu

IPC: H01L29/66 ,  H01L29/167 ,  H01L21/223 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/45 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/165 ,  H01L29/08

Abstract: A method includes forming a fin structure over a substrate; forming a source/drain structure adjoining the fin structure, in which the source/drain structure includes tin; and exposing the source/drain structure to a boron-containing gas to diffuse boron into the source/drain structure to form a doped region in the source/drain structure.

公开(公告)号：US12211897B2

公开(公告)日：2025-01-28

申请号：US18362778

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Chung-En Tsai ,  Chia-Che Chung ,  Chee-Wee Liu ,  Fang-Liang Lu ,  Yu-Shiang Huang ,  Hung-Yu Yeh ,  Chien-Te Tu ,  Yi-Chun Liu

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: The present disclosure provides a semiconductor device with a plurality of semiconductor channel layers. The semiconductor channel layers include a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer. A strain in the second semiconductor layer is different from a strain in the first semiconductor layer. A gate is disposed over the plurality of semiconductor channel layers.

公开(公告)号：US20220246726A1

公开(公告)日：2022-08-04

申请号：US17162896

申请日：2021-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. MORE ,  Cheng-Han Lee ,  Shih-Chieh Chang ,  Shih-Ya Lin ,  Chung-En Tsai ,  Chee-Wee Liu

IPC: H01L29/161 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40

Abstract: The present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. The buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. The semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. The epitaxial structure includes germanium and tin.

公开(公告)号：US10340383B2

公开(公告)日：2019-07-02

申请号：US15277079

申请日：2016-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Huang-Siang Lan ,  CheeWee Liu ,  Chi-Wen Liu ,  Shih-Hsien Huang ,  I-Hsieh Wong ,  Hung-Yu Yeh ,  Chung-En Tsai

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm−3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.

公开(公告)号：US11631768B2

公开(公告)日：2023-04-18

申请号：US16459511

申请日：2019-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Huang-Siang Lan ,  CheeWee Liu ,  Chi-Wen Liu ,  Shih-Hsien Huang ,  I-Hsieh Wong ,  Hung-Yu Yeh ,  Chung-En Tsai

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L27/092 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8238

Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm−3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.