公开(公告)号：US11749328B2

公开(公告)日：2023-09-05

申请号：US17871983

申请日：2022-07-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Zong-You Luo ,  Ya-Jui Tsou ,  Chee-Wee Liu ,  Shao-Yu Lin ,  Liang-Chor Chung ,  Chih-Lin Wang

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: G11C11/161 ,  H10B61/00 ,  H10B61/20 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.

公开(公告)号：US20230207634A1

公开(公告)日：2023-06-29

申请号：US18178893

申请日：2023-03-06

Applicant: Taiwan Semiconductor Manufacturing co., Ltd.

Inventor： Shahaji B. More ,  Cheng-Han Lee ,  Shih-Chieh Chang ,  Shih-Ya Lin ,  Chung-En Tsai ,  Chee-Wee Liu

IPC: H01L29/161 ,  H01L29/786 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/161 ,  H01L29/78696 ,  H01L29/401 ,  H01L29/66742 ,  H01L29/42392

Abstract: The present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. The buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. The semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. The epitaxial structure includes germanium and tin.

公开(公告)号：US11600703B2

公开(公告)日：2023-03-07

申请号：US17162896

申请日：2021-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Cheng-Han Lee ,  Shih-Chieh Chang ,  Shih-Ya Lin ,  Chung-En Tsai ,  Chee-Wee Liu

IPC: H01L29/161 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40

Abstract: The present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. The buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. The semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. The epitaxial structure includes germanium and tin.

公开(公告)号：US11411082B2

公开(公告)日：2022-08-09

申请号：US16590156

申请日：2019-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd. ,  National Taiwan University

Inventor： Ya-Jui Tsou ,  Zong-You Luo ,  Wen Hung Huang ,  Jhih-Yang Yan ,  Chee-Wee Liu

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

Abstract: The current disclosure describes techniques for individually selecting the number of channel strips for a device. The channel strips are selected by defining a three-dimensional active region that include a surface active area and a depth/height. Semiconductor strips in the active region are selected as channel strips. Semiconductor strips contained in the active region will be configured to be channel strips. Semiconductor strips not included in the active region are not selected as channel strips and are separated from source/drain structures by an auxiliary buffer layer.

公开(公告)号：US12249604B2

公开(公告)日：2025-03-11

申请号：US18360416

申请日：2023-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Chih-Hsiung Huang ,  Chung-En Tsai ,  Chee-Wee Liu ,  Kun-Wa Kuok ,  Yi-Hsiu Hsiao

IPC: H01L29/40 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.

公开(公告)号：US11776998B2

公开(公告)日：2023-10-03

申请号：US17582731

申请日：2022-01-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Chung-En Tsai ,  Chia-Che Chung ,  Chee-Wee Liu ,  Fang-Liang Lu ,  Yu-Shiang Huang ,  Hung-Yu Yeh ,  Chien-Te Tu ,  Yi-Chun Liu

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/0262 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02609 ,  H01L21/30604 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78696

Abstract: A device comprises a plurality of nanosheets, source/drain stressors, and a gate structure wrapping around the nanosheets. The nanosheets extend in a first direction above a semiconductor substrate and are arranged in a second direction substantially perpendicular to the first direction. The source/drain stressors are on either side of the nanosheets. Each of the source/drain stressors comprises a first epitaxial layer and a second epitaxial layer over the first epitaxial layer. The first and second epitaxial layers are made of a Group IV element and a Group V element. An atomic ratio of the Group V element to the Group IV element in the second epitaxial layer is greater than an atomic ratio of the Group V element to the Group IV element in the first epitaxial layer.

公开(公告)号：US11177430B2

公开(公告)日：2021-11-16

申请号：US16443772

申请日：2019-06-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Ya-Jui Tsou ,  Zong-You Luo ,  Chee-Wee Liu ,  Shao-Yu Lin ,  Liang-Chor Chung ,  Chih-Lin Wang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16

Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer and a reference layer over the pinned layer. The SOT layer is spaced apart from the memory stack. The free layer is over the memory stack and the SOT layer.

公开(公告)号：US12211897B2

公开(公告)日：2025-01-28

申请号：US18362778

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Chung-En Tsai ,  Chia-Che Chung ,  Chee-Wee Liu ,  Fang-Liang Lu ,  Yu-Shiang Huang ,  Hung-Yu Yeh ,  Chien-Te Tu ,  Yi-Chun Liu

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: The present disclosure provides a semiconductor device with a plurality of semiconductor channel layers. The semiconductor channel layers include a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer. A strain in the second semiconductor layer is different from a strain in the first semiconductor layer. A gate is disposed over the plurality of semiconductor channel layers.

公开(公告)号：US20240120409A1

公开(公告)日：2024-04-11

申请号：US18525131

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd. ,  National Taiwan University

Inventor： Miin-Jang Chen ,  Kuen-Yu Tsai ,  Chee-Wee Liu

IPC: H01L29/66 ,  H01L21/308

CPC classification number: H01L29/66795 ,  H01L21/3086 ,  H01L21/31144

Abstract: A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.

公开(公告)号：US11864369B2

公开(公告)日：2024-01-02

申请号：US17691879

申请日：2022-03-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Hung-Yu Ye ,  Chung-Yi Lin ,  Yun-Ju Pan ,  Chee-Wee Liu

IPC: H01L27/11 ,  H01L29/66 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786 ,  H01L23/535 ,  H01L21/324 ,  H01L21/8238 ,  H10B10/00

CPC classification number: H10B10/125 ,  H01L21/3247 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/823885 ,  H01L23/535 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: A device includes a first horizontal-gate-all-around (HGAA) transistor, a second HGAA transistor, a first vertical-gate-all-around (VGAA) transistor, and a second VGAA transistor. The first HGAA transistor and the second HGAA transistor are adjacent to each other. The first VGAA transistor is over the first HGAA transistor. The second VGAA transistor is over the second HGAA transistor. A top surface of the first VGAA transistor is substantially coplanar with a top surface of the second VGAA transistor.