公开(公告)号：US11600623B2

公开(公告)日：2023-03-07

申请号：US16657421

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC: H01L27/11 ,  G11C11/412 ,  G06F30/30

Abstract: Well pick-up regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a circuit region; a first well pick-up (WPU) region; a first well oriented lengthwise along a first direction in the circuit region and extending into the first WPU region, the first well having a first conductivity type; and a second well oriented lengthwise along the first direction in the circuit region and extending into the first WPU region, the second well having a second conductivity type different from the first conductivity type, wherein the first well has a first portion in the circuit region and a second portion in the first WPU region, and the second portion of the first well has a width larger than the first portion of the first well along a second direction perpendicular to the first direction.

公开(公告)号：US20220359536A1

公开(公告)日：2022-11-10

申请号：US17873626

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC: H01L27/11 ,  G11C11/412 ,  G06F30/30

Abstract: Well pick-up (WPU) regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a circuit region, a WPU region, a first well extending lengthwise along a first direction through the circuit region and into the WPU region, a second well extending lengthwise along the first direction through the circuit region and into the WPU region, and a third well physically connecting a portion of the first well in the WPU region and a portion of the second well in the WPU region.

公开(公告)号：US20220352365A1

公开(公告)日：2022-11-03

申请号：US17812874

申请日：2022-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Kuo-Hsiu Hsu ,  Feng-Ming Chang ,  Kian-Long Lim ,  Lien Jung Hung

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L27/088 ,  H01L29/66 ,  H01L29/16

Abstract: A semiconductor device including nanosheet field-effect transistors (NSFETs) in a first region and fin field-effect transistors (FinFETs) in a second region and methods of forming the same are disclosed. In an embodiment, a device includes a first memory cell, the first memory cell including a first transistor including a first channel region, the first channel region including a first plurality of semiconductor nanostructures; and a second transistor including a second channel region, the second channel region including a semiconductor fin.

公开(公告)号：US11450673B2

公开(公告)日：2022-09-20

申请号：US16945146

申请日：2020-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Chia-Hao Pao ,  Yu-Kuan Lin ,  Lien Jung Hung ,  Ping-Wei Wang ,  Shih-Hao Lin

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L27/11 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

公开(公告)号：US20220285369A1

公开(公告)日：2022-09-08

申请号：US17750649

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Kian-Long Lim ,  Chih-Chuan Yang ,  Chia-Hao Pao ,  Jing-Yi Lin

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238

Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.

公开(公告)号：US20220246465A1

公开(公告)日：2022-08-04

申请号：US17682425

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Chang-Ta Yang

IPC: H01L21/762 ,  H01L21/3065 ,  H01L27/11

Abstract: A method includes receiving a structure that includes a substrate including a first well region having a first dopant type and a second well region having a second dopant type that is opposite to the first dopant type; and fins extending above the substrate. The method further includes forming a patterned etch mask on the structure, wherein the patterned etch mask provides an opening that is directly above a first fin of the fins, wherein the first fin is directly above the first well region. The method further includes etching the structure through the patterned etch mask, wherein the etching removes the first fin and forms a recess in the substrate that spans from the first well region into the second well region; and forming a dielectric material between remaining portions of the fins and within the recess.

公开(公告)号：US11367479B2

公开(公告)日：2022-06-21

申请号：US16942278

申请日：2020-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Shih-Hao Lin

IPC: G11C16/04 ,  G11C11/412 ,  H01L21/475 ,  H01L27/11 ,  G11C11/419

Abstract: Semiconductor devices and methods are provided. A semiconductor device of the present disclosure includes a bias source, a memory cell array including a first region adjacent to the bias source and a second region away from the bias source, and a conductive line electrically coupled to the bias source, a first memory cell in the first region and a second memory cell in the second region. The first memory cell is characterized by a first alpha ratio and the second memory cell is characterized by a second alpha ratio smaller than the first alpha ratio.

公开(公告)号：US20210272966A1

公开(公告)日：2021-09-02

申请号：US17036487

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Chih-Chuan Yang ,  Hsin-Wen Su ,  Kian-Long Lim ,  Chien-Chih Lin

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238

Abstract: An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.

公开(公告)号：US12160985B2

公开(公告)日：2024-12-03

申请号：US18151991

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Wei Wang ,  Chih-Chuan Yang ,  Lien Jung Hung ,  Feng-Ming Chang ,  Kuo-Hsiu Hsu ,  Kian-Long Lim ,  Ruey-Wen Chang

IPC: G11C11/41 ,  G11C11/418 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B10/00

Abstract: Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.

公开(公告)号：US20240379851A1

公开(公告)日：2024-11-14

申请号：US18780748

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Wen Su ,  Yu-Kuan Lin ,  Chih-Chuan Yang ,  Chang-Ta Yang ,  Shih-Hao Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762

Abstract: A semiconductor device includes a memory macro having a middle strap area between edges of the memory macro and memory bit areas on both sides of the middle strap area. The memory macro includes n-type wells and p-type wells arranged alternately along a first direction with well boundaries between the adjacent n-type and p-type wells. The n-type and the p-type wells extend lengthwise along a second direction and extend continuously through the middle strap area and the memory bit areas. The memory macro includes a first dielectric layer disposed at the well boundaries in the middle strap area and the memory bit areas. From a top view, the first dielectric layer extends along the second direction and fully separates the n-type wells from the p-type wells in the middle strap area. From a cross-sectional view, the first dielectric layer vertically extends into the n-type or the p-type wells.