公开(公告)号：US20190131392A1

公开(公告)日：2019-05-02

申请号：US16217102

申请日：2018-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Yen-Ming Chen ,  Feng-Cheng Yang

IPC: H01L29/06 ,  H01L21/306 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/08

Abstract: Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.

公开(公告)号：US20240178271A1

公开(公告)日：2024-05-30

申请号：US18433217

申请日：2024-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Yen-Ming Chen ,  Feng-Cheng Yang

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/02057 ,  H01L21/02227 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851 ,  H01L21/3065

Abstract: Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.

公开(公告)号：US11810825B2

公开(公告)日：2023-11-07

申请号：US17411937

申请日：2021-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L27/088 ,  H01L29/06 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66545

Abstract: A method of fabricating a fin-like field effect transistor (FinFET) device includes providing a semiconductor substrate having a region for forming p-type metal-oxide-semiconductor (PMOS) devices and a region for forming n-type metal-oxide-semiconductor (PMOS) devices, forming fin structures in both regions of the substrate separated by isolation features, first forming source/drain (S/D) features in the PMOS region, and subsequently forming S/D features in the NMOS region. First forming the PMOS S/D features and then forming the NMOS S/D features results in a greater extent of loss of isolation features in the PMOS region than in the NMOS region.

公开(公告)号：US20220352353A1

公开(公告)日：2022-11-03

申请号：US17869704

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Chung-Chi WEN ,  Wei-Yuan LU ,  Feng-Cheng YANG ,  Yen-Ming CHEN

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06

Abstract: A method for fabricating a semiconductor device that includes a merged source/drain feature extending between two adjacent fin structures is provided. An air gap is formed under the merged source/drain feature. Forming the epitaxial feature includes growing a first epitaxial feature having a first portion over the first fin structure and a second portion over the second fin structure, growing a second epitaxial feature over the first and second portions of the first epitaxial feature, and growing a third epitaxial feature over the second epitaxial feature. The second epitaxial feature includes a merged portion between the first fin structure and the second fin structure.

公开(公告)号：US20220069135A1

公开(公告)日：2022-03-03

申请号：US17321996

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Chung-Chi Wen ,  Chia-Pin Lin

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor according one embodiment of the present disclosure include a plurality of channel members disposed over a substrate, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a source/drain feature. The source/drain feature includes a first epitaxial layer in contact with the substrate and the plurality of channel members, and a second epitaxial layer in contact with the first epitaxial layer and the plurality of inner spacer features. The first epitaxial layer and the second epitaxial layer include silicon germanium. A germanium content of the second epitaxial layer is greater than a germanium content of the first epitaxial layer.

公开(公告)号：US20210384081A1

公开(公告)日：2021-12-09

申请号：US17411937

申请日：2021-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L27/088 ,  H01L29/06 ,  H01L27/092

Abstract: A method of fabricating a fin-like field effect transistor (FinFET) device includes providing a semiconductor substrate having a region for forming p-type metal-oxide-semiconductor (PMOS) devices and a region for forming n-type metal-oxide-semiconductor (PMOS) devices, forming fin structures in both regions of the substrate separated by isolation features, first forming source/drain (S/D) features in the PMOS region, and subsequently forming S/D features in the NMOS region. First forming the PMOS S/D features and then forming the NMOS S/D features results in a greater extent of loss of isolation features in the PMOS region than in the NMOS region.

公开(公告)号：US20210272848A1

公开(公告)日：2021-09-02

申请号：US16887273

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Chia-Pin Lin

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/308 ,  H01L29/08 ,  H01L27/088

Abstract: A method includes etching two source/drain regions over a substrate to form two source/drain trenches; epitaxially growing two source/drain features in the two source/drain trenches respectively; performing a cut process to the two source/drain features; and after the cut process, depositing a contact etch stop layer (CESL) over the two source/drain features.

公开(公告)号：US11088245B2

公开(公告)日：2021-08-10

申请号：US17001464

申请日：2020-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Yen-Ming Chen ,  Feng-Cheng Yang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02 ,  H01L29/78 ,  H01L21/306 ,  H01L21/3065

Abstract: Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.

公开(公告)号：US20200381310A1

公开(公告)日：2020-12-03

申请号：US16994331

申请日：2020-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/265 ,  H01L27/092 ,  H01L29/167 ,  H01L29/66

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first device region and a second device region, a first fin over the substrate in the first device region, a second fin over the substrate in the second device region, a first epitaxial feature over the first fin in the source/drain region of the first fin, a second epitaxial feature over the second fin in the source/drain region of the second fin, and a dielectric layer on the first and second epitaxial features. The first epitaxial feature is doped with a first dopant of a first conductivity and the second epitaxial feature is doped with a second dopant of a second conductivity different from the first conductivity. The dielectric layer is doped with the first dopant.

公开(公告)号：US10748820B2

公开(公告)日：2020-08-18

申请号：US16717426

申请日：2019-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/167 ,  H01L27/092 ,  H01L21/265 ,  H01L29/78 ,  H01L29/165 ,  H01L29/08 ,  H01L21/762 ,  H01L21/3115 ,  H01L21/308 ,  H01L21/027

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first device region and a second device region, a first fin over the substrate in the first device region, a second fin over the substrate in the second device region, a first epitaxial feature over the first fin in the source/drain region of the first fin, a second epitaxial feature over the second fin in the source/drain region of the second fin, and a dielectric layer on the first and second epitaxial features. The first epitaxial feature is doped with a first dopant of a first conductivity and the second epitaxial feature is doped with a second dopant of a second conductivity different from the first conductivity. The dielectric layer is doped with the first dopant.