公开(公告)号：US20230387108A1

公开(公告)日：2023-11-30

申请号：US18362030

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Te LIN ,  Wei-Yuan LU ,  Feng-Cheng YANG

IPC: H01L27/088 ,  H01L23/522 ,  H01L23/48 ,  H01L29/06 ,  H01L27/06 ,  H01L29/66 ,  H01L21/8234 ,  H10B10/00 ,  H10B61/00 ,  H10N59/00

CPC classification number: H01L27/088 ,  H01L23/5226 ,  H01L23/481 ,  H01L29/0653 ,  H01L27/0688 ,  H01L29/66545 ,  H01L28/40 ,  H01L21/823475 ,  H01L23/5222 ,  H10B10/12 ,  H10B61/00 ,  H10N59/00 ,  H01L21/8258

Abstract: A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.

公开(公告)号：US20230369490A1

公开(公告)日：2023-11-16

申请号：US18346480

申请日：2023-07-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang LEE ,  Ting-Yeh CHEN ,  Chii-Horng LI ,  Feng-Cheng YANG

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/0847

Abstract: A method includes forming a fin in a substrate. The fin is etched to create a source/drain recess. A source/drain feature is formed in the source/drain recess, in which a lattice constant of the source/drain feature is greater than a lattice constant of the fin. An epitaxy coat is grown over the source/drain feature, in which a lattice constant of the epitaxy coat is smaller than a lattice constant of the fin.

公开(公告)号：US20220384654A1

公开(公告)日：2022-12-01

申请号：US17818230

申请日：2022-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching CHU ,  Wei-Yang LEE ,  Feng-Cheng YANG ,  Yen-Ming CHEN

IPC: H01L29/78 ,  H01L29/08

Abstract: Methods and devices formed thereof that include a fin structure extending from a substrate and a gate structure is formed over the fin structure. An epitaxial feature is formed over the fin structure adjacent the gate structure. The epitaxial feature can include a hollow region (or dielectric filled hollow region) in the epitaxial source/drain region. A selective etching process is performed to remove at least a portion of an epitaxial region having a second dopant type to form the hollow area between the first epitaxial portion and the third epitaxial portion.

公开(公告)号：US20220352353A1

公开(公告)日：2022-11-03

申请号：US17869704

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Chung-Chi WEN ,  Wei-Yuan LU ,  Feng-Cheng YANG ,  Yen-Ming CHEN

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06

Abstract: A method for fabricating a semiconductor device that includes a merged source/drain feature extending between two adjacent fin structures is provided. An air gap is formed under the merged source/drain feature. Forming the epitaxial feature includes growing a first epitaxial feature having a first portion over the first fin structure and a second portion over the second fin structure, growing a second epitaxial feature over the first and second portions of the first epitaxial feature, and growing a third epitaxial feature over the second epitaxial feature. The second epitaxial feature includes a merged portion between the first fin structure and the second fin structure.

公开(公告)号：US20210257482A1

公开(公告)日：2021-08-19

申请号：US16949728

申请日：2020-11-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching CHU ,  Chung-Chi WEN ,  Wei-Yuan LU ,  Feng-Cheng YANG ,  Yen-Ming CHEN

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234

Abstract: A method for fabricating a semiconductor device that includes a merged source/drain feature extending between two adjacent fin structures. An air gap is formed under the merged source/drain feature. Forming the epitaxial feature includes growing a first epitaxial feature having a first portion over the first fin structure and a second portion over the second fin structure, growing a second epitaxial feature over the first and second portions of the first epitaxial feature, and growing a third epitaxial feature over the second epitaxial feature. The second epitaxial feature includes a merged portion between the first fin structure and the second fin structure.

公开(公告)号：US20190148519A1

公开(公告)日：2019-05-16

申请号：US15875485

申请日：2018-01-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Hsuan LEE ,  Bo-Yu LAI ,  Chi-On CHUI ,  Cheng-Yu YANG ,  Yen-Ting CHEN ,  Sai-Hooi YEONG ,  Feng-Cheng YANG ,  Yen-Ming CHEN

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L21/306 ,  H01L21/762

Abstract: A semiconductor device and a method for forming the same are provided. The method includes forming a gate structure over a fin structure. The method further includes forming first gate spacers on opposite sidewalls of the gate structure. The method further includes forming source/drain features in the fin structure and adjacent to the first gate spacers. The method further includes performing a surface treatment process on top surfaces of the source/drain features and outer sidewalls of the first gate spacers. The method further includes depositing a contact etch stop layer (CESL) over the source/drain features and the first gate spacers. A first portion of the CESL is deposited over the top surfaces of the source/drain features at a first deposition rate. A second portion of the CESL is deposited over the outer sidewalls of the first gate spacers at a second deposition rate.

公开(公告)号：US20190096880A1

公开(公告)日：2019-03-28

申请号：US15715310

申请日：2017-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Te LIN ,  Wei-Yuan LU ,  Feng-Cheng YANG

IPC: H01L27/088 ,  H01L29/06 ,  H01L23/48 ,  H01L23/522

Abstract: A semiconductor device is provided. The semiconductor device includes a first transistor, a first interconnect structure, and a second transistor. The first transistor has a first gate length. The first interconnect structure is over the first transistor. The second transistor is over the first interconnect structure. The second transistor is electrically coupled to the first transistor through the first interconnect structure. The second transistor has a second gate length, and the first gate length is shorter than the second gate length.

公开(公告)号：US20240088155A1

公开(公告)日：2024-03-14

申请号：US18510370

申请日：2023-11-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Bo-Yu LAI ,  Kai-Hsuan LEE ,  Wei-Yang LEE ,  Feng-Cheng YANG ,  Yen-Ming CHEN

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/0653 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/31111

Abstract: A semiconductor device includes source/drain regions, a gate structure, a first gate spacer, and a dielectric material. The source/drain regions are over a substrate. The gate structure is laterally between the source/drain regions. The first gate spacer is on a first sidewall of the gate structure, and spaced apart from a first one of the source/drain regions at least in part by a void region. The dielectric material is between the first one of the source/drain regions and the void region. The dielectric material has a gradient ratio of a first chemical element to a second chemical element.

公开(公告)号：US20220384442A1

公开(公告)日：2022-12-01

申请号：US17885383

申请日：2022-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Bo-Yu LAI ,  Kai-Hsuan LEE ,  Wei-Yang LEE ,  Feng-Cheng YANG ,  Yen-Ming CHEN

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234

Abstract: A semiconductor device includes a gate stack, an epitaxy structure, a first spacer, a second spacer, and a dielectric residue. The gate stack is over a substrate. The epitaxy structure is formed raised above the substrate. The first spacer is on a sidewall of the gate stack. The first spacer and the epitaxy structure define a void therebetween. The second spacer seals the void between the first spacer and the epitaxy structure. The dielectric residue is in the void and has an upper portion and a lower portion under the upper portion. The upper portion of the dielectric residue has a silicon-to-nitrogen atomic ratio higher than a silicon-to-nitrogen atomic ratio of the lower portion of the dielectric residue.

公开(公告)号：US20200135590A1

公开(公告)日：2020-04-30

申请号：US16412007

申请日：2019-05-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Bo-Yu LAI ,  Kai-Hsuan LEE ,  Wei-Yang LEE ,  Feng-Cheng YANG ,  Yen-Ming CHEN

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L27/092

Abstract: A method includes forming a gate stack over a semiconductor substrate, forming a first spacer layer on a sidewall of the gate stack, forming a sacrificial spacer film over the first spacer layer, forming an epitaxy structure on the semiconductor substrate, and performing an etching process on the sacrificial spacer film to form a gap between the first spacer layer and the epitaxy structure. An outer portion of the sacrificial spacer film has a topmost end higher than that of an inner portion of the sacrificial spacer film after performing the etching process. The method further includes forming a second spacer layer to seal the gap between the epitaxy structure and the first spacer layer.