公开(公告)号：US20220208989A1

公开(公告)日：2022-06-30

申请号：US17699362

申请日：2022-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Chung-I Yang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/417

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes channel members disposed over a substrate, a gate structure engaging the channel members, and an epitaxial feature adjacent the channel members. At least one of the channel members has an end portion in physical contact with an outer portion of the epitaxial feature. The end portion of the at least one of the channel members includes a first dopant of a first concentration. The outer portion of the epitaxial feature includes a second dopant of a second concentration. The first concentration is higher than the second concentration.

公开(公告)号：US11362001B2

公开(公告)日：2022-06-14

申请号：US16911665

申请日：2020-06-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsiao-Han Liu ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Shi-Ning Ju ,  Kuan-Lun Cheng

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first fin structure, a second fin structure, a third fin structure, and a fourth fin structure formed over a substrate. The semiconductor structure further includes first nanostructures, second nanostructures, third nanostructures, and fourth nanostructures. The semiconductor structure further includes a first gate structure wrapping around the first nanostructures and the second nanostructures, and a second gate structure wrapping around the third nanostructures and the fourth nanostructures. In addition, a first lateral distance between the first fin structure and the second fin structure is shorter than a second lateral distance between the third fin structure and the fourth fin structure, and the first fin structure and the second fin structure are narrower than the third fin structure and the fourth fin structure.

公开(公告)号：US20220181496A1

公开(公告)日：2022-06-09

申请号：US17682806

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wei Tsai ,  Yi-Bo Liao ,  Sai-Hooi Yeong ,  Hou-Yu Chen ,  Yu-Xuan Huang ,  Kuan-Lun Cheng

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/324 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device according to the present disclosure includes an anti-punch-through (APT) region over a substrate, a plurality of channel members over the APT region, a gate structure wrapping around each of the plurality of channel members, a source/drain feature adjacent to the gate structure, and a diffusion retardation layer. The source/drain feature is spaced apart from the APT region by the diffusion retardation layer. The source/drain feature is spaced apart from each of the plurality of channel members by the diffusion retardation layer. The diffusion retardation layer is a semiconductor material.

公开(公告)号：US11355398B2

公开(公告)日：2022-06-07

申请号：US17027282

申请日：2020-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuan-Ting Pan ,  Kuo-Cheng Chiang ,  Shang-Wen Chang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/768

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer.

公开(公告)号：US20220130976A1

公开(公告)日：2022-04-28

申请号：US17572267

申请日：2022-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Hsing Hsu ,  Sai-Hooi Yeong ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Min Cao

IPC: H01L29/51 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/02

Abstract: A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer.

公开(公告)号：US11316023B2

公开(公告)日：2022-04-26

申请号：US16901572

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/08 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78

Abstract: A method includes providing two structures over a substrate and a source/drain (S/D) contact between the structures. Each structure includes a gate, two gate spacers on opposing sidewalls of the gate, and a first capping layer over the gate and the gate spacers. The method further includes recessing the S/D contact to form a trench, in which a top surface of the S/D contact is below a top surface of the gate spacers. The method further includes depositing an inhibitor layer on the S/D contact but not on surfaces of the first capping layer and not on top surfaces of the gate spacers; depositing a liner layer over top and sidewall surfaces of the first capping layer and surfaces of the gate spacers that are exposed in the trench, wherein the liner layer is free from at least a central portion of the inhibitor layer; and removing the inhibitor layer.

公开(公告)号：US11289583B2

公开(公告)日：2022-03-29

申请号：US16453799

申请日：2019-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Chi-On Chui ,  Kai-Hsuan Lee ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes providing a substrate; forming mandrel patterns over the substrate; forming sacrificial patterns in openings between the mandrel patterns; removing the mandrel patterns; forming a dielectric layer in openings between the sacrificial patterns; removing the sacrificial patterns, resulting in a plurality of trenches; and forming a gate stack in each of the plurality of trenches.

公开(公告)号：US20220085185A1

公开(公告)日：2022-03-17

申请号：US17533277

申请日：2021-11-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Ning Yao ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Wei-Yang Lee ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/49 ,  H01L29/423 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/417

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin formed on a substrate; and a gate structure disposed over a channel region of the semiconductor fin, the gate structure including a gate dielectric layer and a gate electrode, wherein the gate dielectric layer includes a bottom portion and a side portion, and the gate electrode is separated from the side portion of the gate dielectric layer by a first air gap.

公开(公告)号：US11257903B2

公开(公告)日：2022-02-22

申请号：US16697647

申请日：2019-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ting Lan ,  Guan-Lin Chen ,  Shi-Ning Ju ,  Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

Abstract: Semiconductor structures and method for manufacturing the same are provided. The method for manufacturing the semiconductor structure includes forming a first fin structure including first semiconductor material layers and second semiconductor material layers alternately stacked over a substrate and forming an isolation structure surrounding the first fin structure. The method for manufacturing the semiconductor structure also includes forming a first capping layer over the isolation structure and covering a top surface and sidewalls of the first fin structure and etching the isolation structure to form a first gap between the first capping layer and a top surface of the isolation structure. The method for manufacturing the semiconductor structure also includes forming a protection layer covering a sidewall of the first capping layer and filling in the first gap.

公开(公告)号：US11239325B2

公开(公告)日：2022-02-01

申请号：US16948712

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: Structures and methods that include a device such as a gate-all-around transistor formed on a frontside and a contact to one terminal of the device from the frontside of the structure and one terminal of the device from the backside of the structure. The backside contact may include selectively etching from the backside a first trench extending to expose a first source/drain structure and a second trench extending to a second source/drain structure. A conductive layer is deposited in the trenches and patterned to form a conductive via to the first source/drain structure.