公开(公告)号：US20220390827A1

公开(公告)日：2022-12-08

申请号：US17716849

申请日：2022-04-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Cheng Chen ,  Huan-Ling Lee ,  Ta-Cheng Lien ,  Chia-Jen Chen ,  Hsin-Chang Lee

IPC: G03F1/26

Abstract: A lithography mask including a substrate, a phase shift layer on the substrate and an etch stop layer is provided. The phase shift layer is patterned and the substrate is protected from etching by the etch stop layer. The etch stop layer can be a material that is semi-transmissive to light used in photolithography processes or it can be transmissive to light used in photolithography processes.

公开(公告)号：US11442356B2

公开(公告)日：2022-09-13

申请号：US16872212

申请日：2020-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Chang Lee ,  Pei-Cheng Hsu ,  Chih-Tao Chien ,  Ming-Wei Chen ,  Ta-Cheng Lien

IPC: G03F1/24 ,  G03F1/38 ,  G03F1/48

Abstract: A multi-layer reflective structure is disposed over the substrate. An amorphous capping layer is disposed over the multi-layer reflective structure. The amorphous capping layer may contain ruthenium, oxygen, niobium, nitrogen, tantalum, or zirconium. An amorphous layer may also be disposed between the multi-layer reflective structure and the amorphous capping layer. The amorphous layer includes amorphous silicon, amorphous silicon oxide, or amorphous silicon nitride.

公开(公告)号：US11385538B2

公开(公告)日：2022-07-12

申请号：US17109878

申请日：2020-12-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Chang Lee ,  Pei-Cheng Hsu ,  Hao-Ping Cheng ,  Ta-Cheng Lien

IPC: G03F1/82 ,  G03F1/64

Abstract: In a method of cleaning a photo mask, the photo mask is placed on a support such that a patterned surface faces down, and an adhesive sheet is applied to edges of a backside surface of the photo mask.

公开(公告)号：US11215918B2

公开(公告)日：2022-01-04

申请号：US16776046

申请日：2020-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Cheng Hsu ,  Chun-Fu Yang ,  Ta-Cheng Lien ,  Hsin-Chang Lee

IPC: G03F1/24 ,  G03F1/70 ,  G03F7/20

Abstract: The present disclosure describes a method of patterning a semiconductor wafer using extreme ultraviolet lithography (EUVL). The method includes receiving an EUVL mask that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further includes patterning the absorber layer to form a trench on the EUVL mask, wherein the trench has a first width above a target width. The method further includes treating the EUVL mask with oxygen plasma to reduce the trench to a second width, wherein the second width is below the target width. The method may also include treating the EUVL mask with nitrogen plasma to protect the capping layer, wherein the treating of the EUVL mask with the nitrogen plasma expands the trench to a third width at the target width.

公开(公告)号：US20210349386A1

公开(公告)日：2021-11-11

申请号：US16872212

申请日：2020-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Chang Lee ,  Pei-Cheng Hsu ,  Chih-Tao Chien ,  Ming-Wei Chen ,  Ta-Cheng Lien

IPC: G03F1/24

Abstract: A multi-layer reflective structure is disposed over the substrate. An amorphous capping layer is disposed over the multi-layer reflective structure. The amorphous capping layer may contain ruthenium, oxygen, niobium, nitrogen, tantalum, or zirconium. An amorphous layer may also be disposed between the multi-layer reflective structure and the amorphous capping layer. The amorphous layer includes amorphous silicon, amorphous silicon oxide, or amorphous silicon nitride.

公开(公告)号：US11119398B2

公开(公告)日：2021-09-14

申请号：US16383570

申请日：2019-04-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Chang Lee ,  Pei-Cheng Hsu ,  Ping-Hsun Lin ,  Ta-Cheng Lien ,  Tzu Yi Wang

IPC: G03F1/22 ,  H01L21/027

Abstract: A photo mask for extreme ultra violet (EUV) lithography includes a substrate having a front surface and a back surface opposite to the front surface, a multilayer Mo/Si stack disposed on the front surface of the substrate, a capping layer disposed on the multilayer Mo/Si stack, an absorber layer disposed on the capping layer, and a backside conductive layer disposed on the back surface of the substrate. The backside conductive layer is made of tantalum boride.