公开(公告)号：US20240096805A1

公开(公告)日：2024-03-21

申请号：US18526445

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Wen Chang ,  Yi-Hsun Chiu ,  Cheng-Chi Chuang ,  Ching-Wei Tsai ,  Wei-Cheng Lin ,  Shih-Wei Peng ,  Jiann-Tyng Tzeng

IPC: H01L23/528 ,  H01L21/02 ,  H01L21/8238 ,  H01L23/00 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L23/5286 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823871 ,  H01L24/05 ,  H01L24/13 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/13026

Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.

公开(公告)号：US20240088141A1

公开(公告)日：2024-03-14

申请号：US18511533

申请日：2023-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung Lin ,  Yi-Hsun Chiu ,  Shang-Wen Chang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/50 ,  H01L27/02

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/50 ,  H01L27/0207

Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.

公开(公告)号：US11862561B2

公开(公告)日：2024-01-02

申请号：US17126509

申请日：2020-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Wen Chang ,  Yi-Hsun Chiu ,  Cheng-Chi Chuang ,  Ching-Wei Tsai ,  Wei-Cheng Lin ,  Shih-Wei Peng ,  Jiann-Tyng Tzeng

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L23/00

CPC classification number: H01L23/5286 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823871 ,  H01L24/05 ,  H01L24/13 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/13026

Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.

公开(公告)号：US11848327B2

公开(公告)日：2023-12-19

申请号：US17373255

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung Lin ,  Shang-Wen Chang ,  Yi-Hsun Chiu

IPC: H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L23/50

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/50 ,  H01L27/0207

Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.

公开(公告)号：US20230013764A1

公开(公告)日：2023-01-19

申请号：US17683944

申请日：2022-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao Chou ,  Yi-Hsun Chiu ,  Shang-Wen Chang ,  Ching-Wei Tsai ,  Chih-Hao Wang ,  Min Cao

IPC: H01L23/522 ,  H01L29/06 ,  H01L29/786 ,  H01L21/8234 ,  H01L23/528

Abstract: Semiconductor devices including backside capacitors and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including a front-side conductive line; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a backside conductive line, the backside conductive line having a line width greater than a line width of the front-side conductive line; and a first capacitor structure coupled to the backside interconnect structure.

公开(公告)号：US20220328363A1

公开(公告)日：2022-10-13

申请号：US17358985

申请日：2021-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao Chou ,  Yi-Hsun Chiu ,  Shang-Wen Chang ,  Ching-Wei Tsai ,  Chih-Hao Wang

IPC: H01L21/66 ,  H01L29/06 ,  H01L29/78 ,  H01L23/50 ,  H01L21/768

Abstract: Methods of forming dual-side super power rails in semiconductor devices, semiconductor devices including the same, and methods of testing the semiconductor devices are disclosed. In an embodiment, a device includes a transistor structure; a front-side interconnect structure on a front side of the transistor structure; and a back-side interconnect structure on a back side of the transistor structure. The front-side interconnect structure includes a front-side power delivery network (PDN) and a front-side input/output (I/O) pin. The back-side interconnect structure includes a back-side PDN.

公开(公告)号：US11342326B2

公开(公告)日：2022-05-24

申请号：US16944025

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsun Chiu ,  Ching-Wei Tsai ,  Yu-Xuan Huang ,  Cheng-Chi Chuang ,  Shang-Wen Chang

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/423 ,  H01L21/768 ,  H01L29/417 ,  H01L29/66 ,  H01L23/535

Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.

公开(公告)号：US20220028743A1

公开(公告)日：2022-01-27

申请号：US16935830

申请日：2020-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chi Chuang ,  Li-Zhen Yu ,  Yi-Hsun Chiu ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate; a metal gate structure disposed over a channel region of the semiconductor fin; a first interlayer dielectric (ILD) layer disposed over a source/drain (S/D) region next to the channel region of the semiconductor fin; and a first conductive feature including a first conductive portion disposed on the metal gate structure and a second conductive portion disposed on the first ILD layer, wherein a top surface of the first conductive portion is below a top surface of the second conductive portion, a first sidewall of the first conductive portion connects a lower portion of a first sidewall of the second conductive portion.

公开(公告)号：US11127631B2

公开(公告)日：2021-09-21

申请号：US16149597

申请日：2018-10-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung Lin ,  Yi-Hsun Chiu ,  Shang-Wen Chang

IPC: H01L23/528 ,  H01L23/535 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/768

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a first epitaxial structure and a second epitaxial structure over a semiconductor substrate. The semiconductor device structure also includes a first conductive via electrically connected to the first epitaxial structure through a conductive contact. The first conductive via is misaligned with the first epitaxial structure. The semiconductor device structure further includes a second conductive via electrically connected to the second epitaxial structure. The second conductive via is aligned with the second epitaxial structure.

公开(公告)号：US11063041B2

公开(公告)日：2021-07-13

申请号：US16583438

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung Lin ,  Shang-Wen Chang ,  Yi-Hsun Chiu

IPC: H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L23/50

Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.