公开(公告)号：US20070106967A1

公开(公告)日：2007-05-10

申请号：US11396660

申请日：2006-04-04

申请人： Yoshio Inoue ,  Takashi Yoneda ,  Masaru Ito

发明人： Yoshio Inoue ,  Takashi Yoneda ,  Masaru Ito

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A method for analyzing a layout for a semiconductor integrated circuit, which includes a plurality of physical devices, to generate physical parameter distribution enabling accurate recognition of changes in transistor characteristics caused by systematic variations. The method includes holding systematic variation tables for physical parameters dependent on the layout of the semiconductor integrated circuit among physical parameters related to characteristics of the semiconductor integrated circuit, analyzing a design layout pattern of the semiconductor integrated circuit and selecting tables corresponding to the plurality of physical devices, and generating a physical parameter distribution based on the selected tables.

摘要翻译： 一种用于分析包括多个物理设备的半导体集成电路的布局的方法，用于生成物理参数分布，使得能够精确地识别由系统变化引起的晶体管特性的变化。 该方法包括：根据与半导体集成电路的特性相关的物理参数中的半导体集成电路的布局，取得物理参数的系统变化表，分析半导体集成电路的设计布局图案，以及选择与多个物理 设备，并且基于所选择的表生成物理参数分布。

公开(公告)号：US07103738B2

公开(公告)日：2006-09-05

申请号：US10647260

申请日：2003-08-26

申请人： Takashi Yoneda ,  Tsutomu Kamiyoshi ,  Hiroshi Benno ,  Shirou Yoshioka ,  Tsuneo Uenishi

发明人： Takashi Yoneda ,  Tsutomu Kamiyoshi ,  Hiroshi Benno ,  Shirou Yoshioka ,  Tsuneo Uenishi

IPC分类号： G06F12/16 ,  G06F12/11

CPC分类号： G06F13/28

摘要： A backup memory, a DMA (direct memory access) controller, and a WDT (watch dog timer) are provided in addition to a CPU (central processing unit), a RAM (random access memory), and a peripheral circuit. The DMA controller exercises control so that respective data of the CPU, RAM and peripheral circuit is saved in the backup memory each time the CPU, being under normal operation, supplies a counter reset signal to the WDT, and so that the data that has been saved in the backup memory is restored to the CPU, the RAM and the peripheral circuit, respectively, if the WDT has detected a program runaway and outputted a time-over signal. Therefore, even in a case where a program runaway has occurred in the CPU, normal operation is permitted to be resumed from midway in the program.

摘要翻译： 除了CPU（中央处理单元），RAM（随机存取存储器）和外围电路之外，还提供备用存储器，DMA（直接存储器访问）控制器和WDT（看门狗定时器）。 DMA控制器进行控制，以使CPU，RAM和外围电路的每个数据都保存在备用存储器中，每当处于正常操作状态的CPU向WDT提供计数器复位信号时， 如果WDT检测到程序失控并输出超时信号，则保存在备份存储器中的数据被分别还原到CPU，RAM和外围电路。 因此，即使在CPU中发生程序失控的情况下，也可以在程序的中途恢复正常的动作。

公开(公告)号：US20050278672A1

公开(公告)日：2005-12-15

申请号：US11014814

申请日：2004-12-20

申请人： Toshikatsu Hosono ,  Takashi Yoneda

发明人： Toshikatsu Hosono ,  Takashi Yoneda

IPC分类号： G06F17/50 ,  H01L21/82 ,  H03K19/00 ,  H03K19/0175

CPC分类号： G06F17/505

摘要： An LSI design method according to the present invention is to estimate a timing uncertainty in an early stage of design for each item of which an influence on timing is uncertain among respective items requiring consideration relating to establishment of timing; and define a timing margin in each design stage by using the timing uncertainty estimation result depending on whether or not an influence of the each item on timing has been determined, followed by proceeding with the design in the respective design stages accordingly. As such, according to the present invention, a timing uncertainty is estimated in an early stage of LSI design, followed by proceeding with the design by using the timing uncertainty as required.

摘要翻译： 根据本发明的LSI设计方法是在与设定定时有关的各个项目的各个项目中对每个项目的每个项目的时间不确定性进行估计的时间不确定性; 并且通过使用定时不确定性估计结果来确定每个设计阶段中的定时裕度，这取决于每个项目对定时的影响是否已被确定，随后在相应的设计阶段中进行设计。 因此，根据本发明，在LSI设计的早期阶段估计时序不确定度，然后根据需要使用定时不确定性进行设计。

公开(公告)号：US20050081171A1

公开(公告)日：2005-04-14

申请号：US10807286

申请日：2004-03-24

申请人： Tetsuo Kawano ,  Satoru Yoshikawa ,  Toshikatsu Hosono ,  Shigenori Ichinose ,  Takashi Yoneda

发明人： Tetsuo Kawano ,  Satoru Yoshikawa ,  Toshikatsu Hosono ,  Shigenori Ichinose ,  Takashi Yoneda

IPC分类号： G06F17/50 ,  G06F9/45 ,  H01L21/82

CPC分类号： G06F17/5031

摘要： OCV coefficients in a path being an analysis target according to the number of gate stages are calculated in a coefficient arithmetically operating unit by canceling off a variation in delay in each gate in accordance with the number of gate stages in the target path, and timing analysis of the target path is performed in a timing analysis unit by using the OCV coefficient with the number of gate stages being considered, whereby a variation degree in the entire path is reduced in accordance with the number of gate stages in the target path, thus making it possible to carry out accurate timing analysis in consideration of the variation in a chip of a semiconductor integrated circuit.

摘要翻译： 根据栅极级的数量，在系数运算单元中计算作为分析对象的路径中的OCV系数，通过根据目标路径中的门级的数量消除每个门的延迟的变化，以及定时分析 通过使用考虑了门级数的OCV系数在定时分析单元中执行目标路径的变化，从而根据目标路径中的门级数减少整个路径的变化程度，从而使 考虑到半导体集成电路的芯片的变化，可以进行准确的时序分析。

公开(公告)号：US06550050B2

公开(公告)日：2003-04-15

申请号：US09799640

申请日：2001-03-07

申请人： Toshikatsu Hosono ,  Takashi Yoneda ,  Miyako Fujita ,  Makoto Wakita

发明人： Toshikatsu Hosono ,  Takashi Yoneda ,  Miyako Fujita ,  Makoto Wakita

IPC分类号： G06F1750

CPC分类号： G06F17/5036 ,  G06F17/5068

摘要： In a method of and an apparatus for designing a semiconductor integrated circuit device, which are capable of causing each waveform rounding to fall within a predetermined limit value without delay calculations at an early stage of the development of the semiconductor integrated circuit device, a wiring path resistance Rpath from an output terminal of a target circuit cell to a next-stage circuit cell and an allowable longest wiring resistance RtL drivable by the target circuit cell are compared. When Rpath is less than or equal to RtL (S4: YES), the sum Rtotal of resistances of wiring loads in a net and RtL are compared. If Rtotal is less than or equal to RtL (S5: YES), then the next-stage circuit cell is judged to be drivable within a predetermined waveform rounding limit value. When Rtotal is greater than RtL (S5: NO), an effective resistance Rw of each wiring load and an allowable longest wiring effective resistance RwL are compared. When Rw is less than or equal to RwL (S6: YES), the waveform rounding at the next-stage circuit cell is judged to fall within a predetermined limit value.

公开(公告)号：US5395201A

公开(公告)日：1995-03-07

申请号：US907244

申请日：1992-07-01

申请人： Megumi Yamashita ,  Takashi Yoneda ,  Takashi Asakura

发明人： Megumi Yamashita ,  Takashi Yoneda ,  Takashi Asakura

IPC分类号： B60P1/64 ,  B65D90/00 ,  B65D90/14 ,  B65D90/18 ,  B60P1/04 ,  B66B9/20

CPC分类号： B65D90/0033 ,  B60P1/6427 ,  B65D90/14 ,  B65D90/18

摘要： A container 1 has a support member 3 which ascends and descends freely and is provided at back of a container body 2, a top connecting member 11 which is fixed at front of the container body 2 and can couple and decouple with a carrier 45, a bottom connecting member 16 which is provided at the front of the container body 2 so as to be able to move and which couples and decouples with the carrier 45, and transmitting members 21, 40 which transmit the movement of the bottom connecting member 16 to the support member 3 and raise and lower the support member 3. When this container 1 is loaded on the carrier 45, it is possible to synchronize the front and back of the container body 2 so that the container 1 remains level by raising the front of the container 1 by lifting the top connecting member 11 at the front of the container body 2 by a member 61 of the carrier 45, and holding the bottom connecting member 16 at the front of the container 1 fixed with respect to the ground, transferring the motion of the bottom connecting member 16 relative to the container body 2 to the support member 3 at the back of the container 1 by the transmitting members 21, 40, and extending the support member 3 at the back of the container 1 down to raise the back of the container 1.

摘要翻译： 容器1具有支撑构件3，其自由地上升和下降并且设置在容器主体2的后面;顶部连接构件11，其固定在容器主体2的前面并可与托架45相耦合和解耦; 底部连接构件16，其设置在容器主体2的前部，以便能够移动并且与托架45进行联接和解耦;以及传递构件21,40，其将底部连接构件16的运动传递到 支撑构件3并且升高和降低支撑构件3.当该容器1被装载在托架45上时，可以使容器主体2的前后同步，使得容器1保持水平， 通过托架45的构件61将容器主体2的前部的顶部连接构件11提升，并且将底部连接构件16保持在相对于地面固定的容器1的前部 底部连接构件16相对于容器主体2在容器1的后部通过传动构件21,40的运动，并将支撑构件3延伸到容器1的后部，以将其提升 容器的背面1。

公开(公告)号：US5234679A

公开(公告)日：1993-08-10

申请号：US866347

申请日：1992-04-10

申请人： Takashi Suenaga ,  Mitsuya Ohashi ,  Takashi Yoneda ,  Yoshiyuki Kobayashi

发明人： Takashi Suenaga ,  Mitsuya Ohashi ,  Takashi Yoneda ,  Yoshiyuki Kobayashi

IPC分类号： C01G41/04

CPC分类号： C01G41/04

摘要： A method of refining tungsten hexafluoride containing molybdenum hexafluoride as an impurity includes the step of contacting the tungsten hexafluoride with at least one metal selected from the group consisting of Mo, W, Cu, Ni, Fe, Co, Zn, Ti, Al, Ca and Mg at a temperature ranging from 100.degree. to 500.degree. C. Molybdenum hexafluoride is efficiently removed from the tungsten hexafluoride by the method.

公开(公告)号：US09567227B2

公开(公告)日：2017-02-14

申请号：US13342524

申请日：2012-01-03

申请人： Yoji Arita ,  Takashi Yoneda

发明人： Yoji Arita ,  Takashi Yoneda

IPC分类号： C01B33/02 ,  C01B33/037 ,  H01L31/18

CPC分类号： C01B33/037 ,  C01B33/02 ,  H01L31/182 ,  Y02E10/546 ,  Y02P70/521

摘要： A process for producing silicon which comprises: bringing molten silicon containing an impurity into contact with molten salt in a vessel to react the impurity contained in the molten silicon with the molten salt; removing the impurity from the system.

摘要翻译： 一种生产硅的方法，包括：使含有杂质的熔融硅与容器中的熔融盐接触，使熔融硅中所含的杂质与熔融盐反应; 从系统中去除杂质。

公开(公告)号：US20130030781A1

公开(公告)日：2013-01-31

申请号：US13639758

申请日：2010-04-07

申请人： Takashi Yoneda ,  Takashi Kamiya ,  Nobuyuki Takahashi ,  Mahito Matsuura ,  Kenji Iriguchi

发明人： Takashi Yoneda ,  Takashi Kamiya ,  Nobuyuki Takahashi ,  Mahito Matsuura ,  Kenji Iriguchi

IPC分类号： G06G7/48

CPC分类号： G05B19/4069 ,  G05B2219/35009 ,  G05B2219/35134 ,  G05B2219/35148 ,  G05B2219/35159 ,  G05B2219/49029 ,  Y02P90/265

摘要： When a material shape model is separated in shear through processing, a shape model of a material in a state of being suspended remains in mid-air, and thus, interference is detected excessively. In order to prevent the excessive detection of interference, in a processing simulation method for generating a shape model of a processed material from a shape model of a material and a shape model of a tool processing area which is defined from a shape model of the tool and a movement path of the tool, the shape model of the material being separated into a plurality of shapes by processing is detected; a material shape to be cut-off is extracted from the separated material shapes; and the extracted material shape to be cut-off is excluded from subject of simulation.

摘要翻译： 当材料形状模型在剪切过程中分离时，悬浮状态下的材料的形状模型保持在空中，因此过大地检测到干扰。 为了防止过度的干涉检测，在从材料的形状模型生成加工材料的形状模型的处理模拟方法和从工具的形状模型定义的工具处理区域的形状模型 和工具的移动路径，检测通过处理分离成多个形状的材料的形状模型; 从分离的材料形状中提取要切断的材料形状; 并且将被截取的提取材料形状排除在模拟对象之外。

公开(公告)号：US20110257778A1

公开(公告)日：2011-10-20

申请号：US13141735

申请日：2008-12-24

申请人： Nobuyuki Takahashi ,  Kenji Iriguchi ,  Takashi Kamiya ,  Takashi Yoneda ,  Mahito Matsuura

发明人： Nobuyuki Takahashi ,  Kenji Iriguchi ,  Takashi Kamiya ,  Takashi Yoneda ,  Mahito Matsuura

IPC分类号： G05B19/4069

CPC分类号： G05B19/4069 ,  G05B2219/35316

摘要： Even in an uncuttable state in which an actual rotational direction of a main spindle is not matched with an actually cuttable main spindle rotational direction of a tool, an interference check between a workpiece and the tool is performed. Accordingly, the cuttable main spindle rotational direction of the selected tool or the uncuttable main spindle rotational direction is compared with each main spindle rotational direction of a working machine during execution of a simulation, and it is determined whether an interference check between the tool blade edge and the workpiece is necessary on the basis of the comparison result. When it is determined that the interference check is not necessary in the step above, the interference check between the tool blade edge and the workpiece is not performed. When it is determined that the interference check is necessary, the interference check between the tool blade edge and the workpiece is performed. When the interference therebetween is present, abnormality is detected.

摘要翻译： 即使在主轴的实际旋转方向与工具的实际可切削主轴旋转方向不匹配的不切割状态下，也能够进行工件与工具之间的干涉检查。 因此，在执行模拟期间，将所选择的工具的可切割的主轴旋转方向或不可切削的主轴旋转方向与作业机械的主主轴旋转方向进行比较，并且确定工具刀刃之间的干涉检查 并且在比较结果的基础上需要工件。 当在上述步骤中确定不需要干涉检查时，不执行刀片刃与工件之间的干涉检查。 当确定需要进行干涉检查时，执行刀片刃和工件之间的干涉检查。 当存在它们之间的干扰时，检测到异常。