公开(公告)号：US20230168900A1

公开(公告)日：2023-06-01

申请号：US17537952

申请日：2021-11-30

Applicant: Texas Instruments Incorporated

Inventor： Robin Osa Hoel ,  Anand Kumar G

IPC: G06F9/4401

CPC classification number: G06F9/4401

Abstract: In described examples, an integrated circuit (IC) includes a first temperature sensor, a processor, a second temperature sensor, and a reset module. The first sensor senses a first body temperature of the IC. The processor asserts a thermal shutdown signal if the first body temperature exceeds a first threshold. In response to the thermal shutdown signal, the second sensor asserts a reset request signal and senses a second body temperature of the IC. If the second body temperature is less than a second threshold, the second sensor asserts a reset end signal. The reset module outputs a system reset signal to the first sensor and the processor if the reset request signal is asserted, and outputs a system recovery signal if the reset end signal is asserted. The first sensor and the processor deactivate if the system reset signal is asserted, and activate if the system recovery signal is asserted.

公开(公告)号：US20230168700A1

公开(公告)日：2023-06-01

申请号：US17683217

申请日：2022-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rinu MATHEW ,  Vineet KHURANA ,  Anand Kumar G ,  Aniruddha PERIYAPATNA NAGENDRA ,  Venkatesh KADLIMATTI ,  Torjus Lyng KALLERUD

IPC: G05F1/46 ,  H02M1/00 ,  G01R17/04

CPC classification number: G05F1/462 ,  H02M1/0012 ,  G01R17/04

Abstract: In an example, a device includes a controller and a direct current (DC)-to-DC converter coupled to the controller and configured to provide a load current to a load. The device also includes a low-dropout (LDO) regulator coupled to the DC-to-DC converter. The controller includes digital logic, and the digital logic is configured to determine the load current. The digital logic is configured to turn on the LDO regulator if the load current is above a predetermined threshold. The digital logic is also configured to turn off the LDO regulator if the load current is below the predetermined threshold.

公开(公告)号：US11650930B2

公开(公告)日：2023-05-16

申请号：US17482676

申请日：2021-09-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Veeramanikandan Raju ,  Anand Kumar G ,  Prachi Mishra

IPC: G06F13/10 ,  G06F12/10

CPC classification number: G06F12/10 ,  G06F13/102 ,  G06F2212/657

Abstract: A computing device, including a processor; a memory, wherein the memory is accessible for memory operations via a range of logical memory addresses; a peripheral interface including a first control register; and a peripheral address remapping module configured to determine that the peripheral interface is unused for interfacing with a peripheral; determine a first memory address for accessing the first control register; determine a first logical memory address, the first logical memory address outside of the range of logical memory addresses for accessing the memory; and map the first logical memory address to the first memory address, wherein the first control register is accessible for memory operations using the first logical memory address.

公开(公告)号：US20230138906A1

公开(公告)日：2023-05-04

申请号：US17566391

申请日：2021-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robin Osa HOEL ,  Anand Kumar G ,  Praveen KUMAR N ,  Aniruddha PERIYAPATNA NAGENDRA ,  Ankitha M

IPC: G06F21/57 ,  G06F21/54 ,  G06F21/79 ,  G06F9/30

Abstract: This disclosure relates to a system that includes a centralized trim controller and a non-volatile memory that includes a trim sector configured for hosting trim data for one or more peripherals. The trim controller is configured to receive, for each of the one or more peripherals, trim values of the one or more peripherals from the trim sector of the nonvolatile memory, and provide the trim values to the one or more peripherals. Some trim values are updateable by receiving a password at the trim controller. If the password is valid, a timeout counter is initiated, during which time the trim value is updateable.

公开(公告)号：US20200319250A1

公开(公告)日：2020-10-08

申请号：US16376697

申请日：2019-04-05

Applicant: Texas Instruments Incorporated

Inventor： Veeramanikandan Raju ,  Anand Kumar G ,  Christy Leigh She

IPC: G01R31/3185 ,  H04L29/06 ,  G06F21/31 ,  G06F21/45

Abstract: A system and method for dynamically protecting against security vulnerabilities in a reconfigurable signal chain. The system includes a signal chain formed from at least a first component connected with a second component. The first component has a set of source outputs and a first authentication block, and the second signal chain component has a set of destination inputs and a second authentication block. The system also includes a signal chain configurator that populates the first authentication block with at least one validated endpoint from the set of destination inputs. A signal chain integrity block, which is communicatively coupled with the first authentication block and the second authentication block, identifies a source-destination pair from one or more endpoint pairs formed from the at least one validated endpoint and the set of source outputs. The signal chain integrity block propagates the source-destination pair to the first authentication block and the second authentication block. The second authentication block authenticates any received input using the source-destination pair.

公开(公告)号：US12266422B2

公开(公告)日：2025-04-01

申请号：US18610993

申请日：2024-03-20

Applicant: Texas Instruments Incorporated

Inventor： Veeramanikandan Raju ,  Anand Kumar G

IPC: G11C7/10 ,  G11C5/14 ,  G11C7/22

Abstract: A communications circuit with an input port, a switching circuit coupled to the input port, and a first and second memory coupled to the switching circuit. The communications circuit also includes controlling circuitry adapted to operate the switching circuit to couple data received at the input port to the first memory while the second memory is disabled from power and to couple data received at the input port to the second memory once the first memory is filled with valid data.

公开(公告)号：US12189471B2

公开(公告)日：2025-01-07

申请号：US18381320

申请日：2023-10-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anand Kumar G

IPC: G06F11/10 ,  G06F11/00 ,  G06F13/00 ,  G06F13/28

Abstract: In an example, a method includes copying data between a source device and a destination device to form first copied data. The method also includes, responsive to completion of the copying, performing a verify-read operation. The verify-read operation includes determining a first checksum of the first copied data, copying the data between the source device and the destination device to form second copied data, determining a second checksum of the second copied data, comparing the first checksum to the second checksum to determine a comparison result, and determining a data integrity validation result based on the comparison result.

公开(公告)号：US20250007892A1

公开(公告)日：2025-01-02

申请号：US18345108

申请日：2023-06-30

Applicant: Texas Instruments Incorporated

Inventor： Veeramanikandan Raju ,  Anand Kumar G

IPC: H04L9/40

Abstract: A network-communicating device with an analog-to-digital converter (ADC) having an output and encryption and selectivity circuitry for encrypting selected output values from the ADC.

公开(公告)号：US12146801B2

公开(公告)日：2024-11-19

申请号：US17355992

申请日：2021-06-23

Applicant: Texas Instruments Incorporated

Inventor： Anand Kumar G

IPC: G01K7/42 ,  G01K1/022 ,  G06F12/16

Abstract: A temperature sensing device for a temperature-based tamper detection system includes an integrated circuit (IC) and a logic circuit. The logic circuit sends an enable signal to the IC, causing it to measure the device temperature, and initiates a security timer. In response to not receiving the device temperature before the security timer expires, the logic circuit outputs a tamper event signal and an error code. The logic circuit can disable the enable signal in response to not receiving the device temperature before the timer expires. In some implementations, the logic circuit is a first logic circuit, and the IC includes an analog integrated circuit (AIC) and a second logic circuit. The second logic circuit receives the enable signal from the first logic circuit, causes the AIC to measure the device temperature, and outputs a ready signal and the device temperature to the first logic circuit.

公开(公告)号：US20240333241A1

公开(公告)日：2024-10-03

申请号：US18194065

申请日：2023-03-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Robin O. Hoel ,  Anand Kumar G ,  Vinheet Khurana ,  Aniruddha Periyapatna Nagendra

IPC: H03G3/30 ,  H04R3/00 ,  H04R29/00

CPC classification number: H03G3/3089 ,  H04R3/00 ,  H04R29/004 ,  H03G2201/103 ,  H04R2430/01

Abstract: Various examples disclosed herein relate to digital signal processing, and more particularly, to identifying metrics of audio samples to dynamically adjust the gain of audio data. In an example embodiment, a pulse density modulation system is provided that includes sample generation circuitry and gain control circuitry coupled to the sample generation circuitry. The sample generation circuitry is configured to sample audio data to produce samples of the audio data and output the samples to a processor and to the gain control circuitry. The gain control circuitry is configured to determine one or more metrics based on the samples of the audio data and output the one or more metrics to the processor.