公开(公告)号：US5890006A

公开(公告)日：1999-03-30

申请号：US989794

申请日：1997-12-12

Applicant: Thang M. Tran ,  Mauricio Calle ,  Shane Southard

Inventor： Thang M. Tran ,  Mauricio Calle ,  Shane Southard

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F13/00

CPC classification number: G06F9/3017 ,  G06F9/30145 ,  G06F9/3842

Abstract: A superscalar microprocessor predecodes instruction data to identify the boundaries of instructions and the type of instruction. In one embodiment, to expedite the dispatch of instructions, the first microcode instruction of the cache line is identified during predecode and stored as a microcode pointer. When the cache line is scanned for dispatch, the microcode pointer is used to identify the first microcode instruction which is conveyed to the MROM unit. In another embodiment, the first scanned instruction is predicted to be a microcode instruction and is dispatched to the MROM unit. A microcode scan circuit uses the microcode pointer and the functional bits of the predecode data to multiplex instruction specific bytes of the first microcode instruction to the MROM unit. If the predicted first microcode instruction is not the actual first microcode instruction, then in a subsequent clock cycle, the actual microcode instruction is dispatched the MROM unit and the incorrectly predicted microcode instruction is canceled.

Abstract translation: 超标量微处理器预处理指令数据以识别指令的边界和指令的类型。 在一个实施例中，为了加快指令的分派，在预解码期间识别高速缓存行的第一微代码指令，并将其存储为微代码指针。 当缓存行被扫描以进行调度时，微代码指针用于识别被传送到MROM单元的第一微代码指令。 在另一个实施例中，预测第一扫描指令是微代码指令，并且被调度到MROM单元。 微代码扫描电路使用微代码指针和预解码数据的功能位将第一微代码指令的指令特定字节复用到MROM单元。 如果预测的第一微代码指令不是实际的第一微代码指令，则在随后的时钟周期中，实际的微代码指令被分派到MROM单元，并且错误地预测的微代码指令被取消。

公开(公告)号：US5881278A

公开(公告)日：1999-03-09

申请号：US550296

申请日：1995-10-30

Applicant: Thang M. Tran ,  Rupaka Mahalingaiah

Inventor： Thang M. Tran ,  Rupaka Mahalingaiah

IPC: G06F9/38 ,  G06F9/32

CPC classification number: G06F9/382 ,  G06F9/30054 ,  G06F9/3806 ,  G06F9/3844 ,  G06F9/3848

Abstract: A return prediction unit is provided which is configured to predict return addresses for return instructions according to a return stack storage included therein. The return stack storage is a stack structure configured to store return addresses associated with previously detected call instructions. Return addresses may be predicted for return instructions early in the instruction processing pipeline of the microprocessor. In one embodiment, the return stack storage additionally stores a call tag and a return tag with each return address. The call tag and return tag respectively identify call and return instructions associated with the return address. These tags may be compared to a branch tag conveyed to the return prediction unit upon detection of a branch misprediction. The results of the comparisons may be used to adjust the contents of the return stack storage with respect to the misprediction. The return prediction unit may continue to predict return addresses correctly following a mispredicted branch instruction.

Abstract translation: 提供返回预测单元，其被配置为根据包括在其中的返回堆栈存储来预测返回指令的返回地址。 返回栈存储器是被配置为存储与先前检测到的调用指令相关联的返回地址的堆栈结构。 可以在微处理器的指令处理流水线的早期为返回指令预测返回地址。 在一个实施例中，返回堆栈存储器另外存储具有每个返回地址的呼叫标签和返回标签。 呼叫标签和返回标签分别标识与返回地址相关联的呼叫和返回指令。 这些标签可以与检测到分支错误预测时传送到返回预测单元的分支标签进行比较。 可以使用比较结果来调整返回堆栈存储器相对于错误预测的内容。 返回预测单元可以继续在错误预测的分支指令之后正确地预测返回地址。

公开(公告)号：US5878255A

公开(公告)日：1999-03-02

申请号：US969039

申请日：1997-11-12

Applicant: Thang M. Tran ,  David B. Witt

Inventor： Thang M. Tran ,  David B. Witt

IPC: G06F9/38 ,  G06F9/40

CPC classification number: G06F9/3844 ,  G06F9/3848

Abstract: An update unit for an array in an integrated circuit is provided. The update unit delays the update of the array until a clock cycle in which the functional input to the array is idle. The input port normally used by the functional input is then used to perform the update. During clock cycles between receiving the update and storing the update into the array, the update unit compares the current functional input address to the update address. If the current functional input address matches the update address, then the update value is provided as the output of the array. Otherwise, the information stored in the indexed storage location is provided. In this manner, the update appears to have been performed in the clock cycle that the update value was received, as in a dual-ported array. A particular embodiment of the update unit is a branch prediction array update unit.

Abstract translation: 提供集成电路中的阵列的更新单元。 更新单元延迟阵列的更新，直到阵列的功能输入空闲的时钟周期为止。 通常由功能输入端使用的输入端口用于执行更新。 在接收到更新并将更新存储到阵列中的时钟周期期间，更新单元将当前功能输入地址与更新地址进行比较。 如果当前功能输入地址与更新地址匹配，则更新值作为数组的输出提供。 否则，提供存储在索引存储位置中的信息。 以这种方式，更新似乎是在接收到更新值的时钟周期中执行的，如双端口阵列中那样。 更新单元的特定实施例是分支预测阵列更新单元。

公开(公告)号：US5875324A

公开(公告)日：1999-02-23

申请号：US947225

申请日：1997-10-08

Applicant: Thang M. Tran ,  David B. Witt

Inventor： Thang M. Tran ,  David B. Witt

IPC: G06F9/38

CPC classification number: G06F9/3844 ,  G06F9/3842 ,  G06F9/3861

Abstract: A superscalar microprocessor employing a branch prediction array update unit is provided. The branch prediction array update unit collects the update prediction information for each branch misprediction or external fetch. When a fetch address is presented for branch prediction, the fetch address is compared to the update address stored in the update unit. If the addresses match, then the update prediction information is forwarded as the output of the array. If the addresses do not match, then the information stored in the indexed storage location is forwarded as the output of the array. When the next external fetch begins or misprediction is detected, the update is written into the branch prediction array. The update unit allows for a single-ported array implementation of the branch prediction array while still maintaining the operational aspects of the dual-ported array implementation, as well as allowing for speculative branch prediction update.

Abstract translation: 提供了采用分支预测阵列更新单元的超标量微处理器。 分支预测阵列更新单元收集每个分支错误预测或外部提取的更新预测信息。 当提取用于分支预测的获取地址时，将获取地址与更新单元中存储的更新地址进行比较。 如果地址匹配，则更新预测信息作为阵列的输出被转发。 如果地址不匹配，则存储在索引存储位置的信息将作为阵列的输出转发。 当检测到下一个外部提取开始或错误预测时，将更新写入分支预测数组。 更新单元允许分支预测阵列的单端口阵列实现，同时仍保持双端口阵列实现的操作方面，以及允许推测分支预测更新。

公开(公告)号：US5864707A

公开(公告)日：1999-01-26

申请号：US570242

申请日：1995-12-11

Applicant: Thang M. Tran ,  Rupaka Mahalingaiah

Inventor： Thang M. Tran ,  Rupaka Mahalingaiah

IPC: G01R31/3185 ,  G06F9/30 ,  G06F9/38 ,  G06F11/267

CPC classification number: G06F9/3806 ,  G06F9/30054 ,  G06F9/30152 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3832 ,  G06F9/3844 ,  G06F9/3848 ,  G01R31/318533 ,  G06F11/2236

Abstract: A microprocessor is provided which is configured to predict return addresses for return instructions according to a return stack storage included therein. The return stack storage is a stack structure configured to store return addresses associated with previously detected call instructions. Return addresses may be predicted for return instructions early in the instruction processing pipeline of the microprocessor. In one embodiment, the return stack storage additionally stores a call tag and a return tag with each return address. The call tag and return tag respectively identify call and return instructions associated with the return address These tags may be compared to a branch tag conveyed to the return prediction unit upon detection of a branch misprediction. The results of the comparisons may be used to adjust the contents of the return stack storage with respect to the misprediction. The microprocessor may continue to predict return addresses correctly following a mispredicted branch instruction.

Abstract translation: 提供微处理器，其被配置为根据其中包括的返回堆栈存储来预测返回指令的返回地址。 返回栈存储器是被配置为存储与先前检测到的调用指令相关联的返回地址的堆栈结构。 可以在微处理器的指令处理流水线的早期为返回指令预测返回地址。 在一个实施例中，返回堆栈存储器另外存储具有每个返回地址的呼叫标签和返回标签。 呼叫标签和返回标签分别标识与返回地址相关联的呼叫和返回指令。这些标签可以与在检测到分支错误预测时传送到返回预测单元的分支标签进行比较。 可以使用比较结果来调整返回堆栈存储器相对于错误预测的内容。 微处理器可以在错误预测的分支指令之后继续正确地预测返回地址。

公开(公告)号：US5850532A

公开(公告)日：1998-12-15

申请号：US814628

申请日：1997-03-10

Applicant: Rammohan Narayan ,  Shane A. Southard ,  Thang M. Tran

Inventor： Rammohan Narayan ,  Shane A. Southard ,  Thang M. Tran

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/00

CPC classification number: G06F9/382 ,  G06F9/30152 ,  G06F9/3816

Abstract: An instruction scanning unit for a superscalar microprocessor is disclosed. The instruction scanning unit processes start, end, and functional byte information (or predecode data) associated with a plurality of contiguous instruction bytes. The processing of start byte information and end byte information is performed independently and in parallel, and the instruction scanning unit produces a plurality of scan values which identify valid instructions within the plurality of contiguous instruction bytes. Additionally, the instruction scanning unit is scaleable. Multiple instruction scanning units may be operated in parallel to process a larger plurality of contiguous instruction bytes. Furthermore, the instruction scanning unit detects error conditions in the predecode data in parallel with scanning to locate instructions. Moreover, in parallel with the error checking and scanning to locate instructions, MROM instructions are located for dispatch to an MROM unit.

Abstract translation: 公开了一种用于超标量微处理器的指令扫描单元。 指令扫描单元处理与多个相邻指令字节相关联的开始，结束和功能字节信息（或预解码数据）。 开始字节信息和结束字节信息的处理是独立且并行执行的，并且指令扫描单元产生多个扫描值，该扫描值标识多个连续指令字节内的有效指令。 另外，指示扫描单元是可扩展的。 可以并行操作多个指令扫描单元以处理较大的多个相邻指令字节。 此外，指令扫描单元与扫描并行地检测预解码数据中的错误状况以定位指令。 此外，与错误检查和扫描并行定位指令，MROM指令位于调度到MROM单元。

公开(公告)号：US5835744A

公开(公告)日：1998-11-10

申请号：US561030

申请日：1995-11-20

Applicant: Thang M. Tran ,  David B. Witt ,  William M. Johnson

Inventor： Thang M. Tran ,  David B. Witt ,  William M. Johnson

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30167 ,  G06F9/3016 ,  G06F9/3824

Abstract: A microprocessor is provided which is configured to locate memory and register operands regardless their use as an A operand or B operand in an instruction. Memory operands are conveyed upon a memory operand bus, and register operands are conveyed upon a register operand bus. Decoding of the source and destination status of the operands may be performed in parallel with the operand fetch. Restricting memory operands to a memory operand bus enables reduced bussing between decode units and the operand fetch unit. After fetching operand values from an operand storage, the operand fetch unit reorders the operand values according to the instruction determined by the associated decode unit. The operand values are thereby properly aligned for conveyance to the associated reservation station.

Abstract translation: 提供微处理器，其被配置为定位存储器和寄存器操作数，而不管它们如何用作指令中的操作数或B操作数。 存储器操作数在存储器操作数总线上传送，并且寄存器操作数在寄存器操作数总线上传送。 操作数的源和目的地状态的解码可以与操作数提取并行执行。 将存储器操作数限制到存储器操作数总线使得能够在解码单元和操作数获取单元之间减少总线。 在从操作数存储器取出操作数值之后，操作数提取单元根据由相关联的解码单元确定的指令对操作数值进行重新排序。 因此，操作数值被适当地对齐以便传送到相关联的保留站。

公开(公告)号：US5822575A

公开(公告)日：1998-10-13

申请号：US713287

申请日：1996-09-12

Applicant: Thang M. Tran

Inventor： Thang M. Tran

IPC: G06F9/32 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/3844

Abstract: A prediction storage for branch predictions and information corresponding to branch instructions which are outstanding within an instruction processing pipeline of a microprocessor. A branch tag is assigned to each branch instruction and the corresponding branch prediction and prediction information is stored into the prediction storage. The branch tag is routed through the instruction processing pipeline with the branch instruction. Branch prediction information corresponding to the instruction remains within the branch prediction storage apparatus, which may be integrated into a branch predictor or coupled nearby. The branch tag may be more easily routed through the pipeline since the branch tag may include fewer bits than the corresponding branch prediction information. The branch prediction information may be updated after correct or incorrect prediction by conveying an indication of the prediction or misprediction and the branch tag of the branch instruction to the branch prediction storage apparatus.

Abstract translation: 用于分支预测的预测存储器和对应于在微处理器的指令处理流水线中突出的分支指令的信息。 分支标签被分配给每个分支指令，并且相应的分支预测和预测信息被存储到预测存储器中。 分支标签通过指令处理流水线与分支指令进行路由。 与指令相对应的分支预测信息保留在分支预测存储装置内，其可以集成到分支预测器中或耦合在附近。 分支标签可以更容易地通过流水线路由，因为分支标签可以包括比相应的分支预测信息少的比特。 可以通过将分支指令的预测或错误预测的指示和分支标签传送到分支预测存储装置，在正确或不正确的预测之后更新分支预测信息。

公开(公告)号：US5813045A

公开(公告)日：1998-09-22

申请号：US685653

申请日：1996-07-24

Applicant: Rupaka Mahalingaiah ,  Thang M. Tran ,  David B. Witt

Inventor： Rupaka Mahalingaiah ,  Thang M. Tran ,  David B. Witt

IPC: G06F9/355 ,  G06F9/38 ,  G06F9/26

CPC classification number: G06F9/355 ,  G06F9/383

Abstract: An apparatus is provided, including one or more early address generation units which attempt to perform data address generation upon decode of an instruction which includes a memory operand. The early address generation units may be successful at generating the data address if the logical data address is formed from a displacement only. Additionally, the early address generation unit may be successful at generating the data address if the logical data address is formed from the displacement and register operands which are available upon decode of the instruction. Data address generation latency may be shortened. If register operands are employed for forming the address and the register operands are not available, the data address may be generated in a functional unit at the execute stage. Therefore, the early address generation mechanism is a conditional mechanism which provides the data address early if the operands are available, and which provides the data address in a more conventional fashion if the operands are not available. In one embodiment, the early address generation units add the displacement value to the segment base address corresponding to the segment register selected by the instruction. The displacement/segment base address addition may be performed while awaiting register operands.

Abstract translation: 提供了一种装置，包括一个或多个早期地址生成单元，其尝试在解码包括存储器操作数的指令时执行数据地址生成。 如果逻辑数据地址仅由位移形成，则早期地址生成单元可以成功地生成数据地址。 此外，如果逻辑数据地址是由指令解码后可用的位移和寄存器操作数形成的，则早期地址生成单元可以成功地生成数据地址。 数据地址生成延迟可能会缩短。 如果使用寄存器操作数来形成地址，并且寄存器操作数不可用，则数据地址可以在执行阶段的功能单元中生成。 因此，早期地址生成机制是一种条件机制，如果操作数可用，则提供数据地址，并且如果操作数不可用，则以更传统的方式提供数据地址。 在一个实施例中，早期地址生成单元将位移值加到对应于由该指令选择的段寄存器的段基地址。 可以在等待寄存器操作数时执行位移/段基址地址添加。

公开(公告)号：US5768555A

公开(公告)日：1998-06-16

申请号：US803093

申请日：1997-02-20

Applicant: Thang M. Tran ,  David B. Witt

Inventor： Thang M. Tran ,  David B. Witt

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3838 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: A reorder buffer is provided which stores a last in buffer (LIB) indication corresponding to each instruction. The last in buffer indication indicates whether or not the corresponding instruction is last, in program order, of the instructions within the buffer to update the storage location defined as the destination of that instruction. The LIB indication is included in the dependency checking comparisons. A dependency is indicated for a given source operand and a destination operand within the reorder buffer if the operand specifiers match and the corresponding LIB indication indicates that the instruction corresponding to the destination operand is last to update the corresponding storage location. At most one of the dependency comparisons for a given source operand can indicate dependency. According to one embodiment, the reorder buffer employs a line-oriented configuration. Concurrently decoded instructions are stored into a line of storage, and the concurrently decoded instructions are retired as a unit. A last in line (LIL) indication is stored for each instruction in the line. The LIL indication indicates whether or not the instruction is last within the line storing that instruction to update the storage location defined as the destination of that instruction. The LIL indications for a line can be used as write enables for the register file.

Abstract translation: 提供重排序缓冲器，其存储对应于每个指令的最后一个缓冲器（LIB）指示。 缓冲器指示中的最后一个指示是否以缓冲器中的指令的程序顺序最后的相应指令是否更新被定义为该指令的目的地的存储位置。 LIB指示包含在依赖关系检查比较中。 如果操作数指定符匹配，并且对应的LIB指示指示对应于目的地操作数的指令最后更新相应的存储位置，则对重定序缓冲器内的给定源操作数和目的地操作数指示依赖关系。 对于给定的源操作数，最多的一个依赖比较可以表示依赖。 根据一个实施例，重排序缓冲器采用线路定向配置。 同时解码的指令被存储到一行存储器中，同时解码的指令作为一个单元退休。 对于行中的每条指令，存储最后一行（LIL）指示。 LIL指示指示在存储该指令的行的最后一条指令是否更新被定义为该指令的目的地的存储位置。 一行的LIL指示可用作寄存器文件的写使能。