公开(公告)号：US06852590B1

公开(公告)日：2005-02-08

申请号：US10709926

申请日：2004-06-07

申请人： Tzu-Ching Tsai ,  Shih-Chung Chou

发明人： Tzu-Ching Tsai ,  Shih-Chung Chou

IPC分类号： H01L21/8242

CPC分类号： H01L27/10867

摘要： A method of fabricating a deep trench capacitor is described. A substrate having a deep trench therein is provided. A doped region is formed in the substrate at the bottom of the deep trench, a dielectric layer is formed on the bottom surface of the deep trench, and a first conductive layer is formed on the dielectric layer. A collar oxide layer is formed on sidewalls of the deep trench that are not covered by the first conductive layer. A material layer is formed covering the first conductive layer and exposing a portion of the collar oxide layer. The exposed collar oxide layer is removed to expose the substrate. Then, the material layer is removed, and a second conductive layer is formed in the deep trench covering the first conductive layer and the collar oxide layer. In this invention, only the second conductive layer is formed on the first conductive layer for electrically connecting the capacitor and an active device, hence the method is more simple.

摘要翻译： 描述制造深沟槽电容器的方法。 提供其中具有深沟槽的衬底。 在深沟槽的底部的衬底中形成掺杂区域，在深沟槽的底表面上形成介电层，并且在介电层上形成第一导电层。 在深沟槽的不被第一导电层覆盖的侧壁上形成环状氧化物层。 形成覆盖第一导电层并暴露套环氧化物层的一部分的材料层。 去除暴露的环状氧化物层以暴露衬底。 然后，去除材料层，并且在覆盖第一导电层和套环氧化物层的深沟槽中形成第二导电层。 在本发明中，仅在第一导电层上形成第二导电层，用于电连接有源器件，因此该方法更简单。

公开(公告)号：US06815307B1

公开(公告)日：2004-11-09

申请号：US10605217

申请日：2003-09-16

申请人： Ping Hsu ,  Tzu-Ching Tsai

发明人： Ping Hsu ,  Tzu-Ching Tsai

IPC分类号： H01L2120

CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L29/66181

摘要： This invention pertains to a method for making a trench capacitor of DRAM devices. A portion of the collar oxide layer is masked after the second polysilicon deposition and recess etching process. Subsequently, the un-masked collar oxide layer is etched away to form an asymmetric collar oxide structure. The third polysilicon deposition and recess etching process is then carried out to form a third polysilicon stud atop the second polysilicon layer. The asymmetric collar oxide structure has a lower annular portion wrapping the second polysilicon layer and insulating the second polysilicon layer from the substrate, and an upper portion serving as a single-sided spacer for blocking diffusion of dopants from the third polysilicon stud to the substrate.

公开(公告)号：US06706587B1

公开(公告)日：2004-03-16

申请号：US10406371

申请日：2003-04-03

申请人： Tzu-Ching Tsai ,  Hui Min Mao ,  Ying Huan Chuang

发明人： Tzu-Ching Tsai ,  Hui Min Mao ,  Ying Huan Chuang

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L28/84 ,  H01L29/66181

摘要： Method for forming buried plates. The method includes providing a substrate formed with a pad stacked layer on the surface, a bottle trench and a protective layer on the upper sidewalls of the bottle trench, forming a doped hemispherical silicon grain (HSG) layer on the protective layer and the sidewalls and bottom of the bottle trench, removing the hemispherical silicon grain layer on the protective layer without removing the hemispherical silicon grain layer from the lower sidewalls and bottom of the bottle trench, forming a covering layer on the protective layer, and subjecting the doped hemispherical silicon grain layer to drive-in annealing so that ions in the HSG layer diffuse out to the substrate, thereby forming a buried plate within the lower sidewalls of the bottle trench.

摘要翻译： 掩埋板成型方法 该方法包括提供在表面上形成有垫堆叠层的基底，瓶沟槽和瓶沟槽的上侧壁上的保护层，在保护层和侧壁上形成掺杂半球形硅晶粒（HSG）层，以及 在瓶子沟槽的底部，去除保护层上的半球形硅晶粒层，而不从瓶沟槽的下侧壁和底部移除半球状硅晶粒层，在保护层上形成覆盖层，并对掺杂的半球形硅颗粒 层以驱动退火，使得HSG层中的离子扩散到衬底，从而在瓶沟槽的下侧壁内形成掩埋板。

公开(公告)号：US06383936B1

公开(公告)日：2002-05-07

申请号：US09875908

申请日：2001-06-08

申请人： Tzu-Ching Tsai ,  Hung-Hsin Lin

发明人： Tzu-Ching Tsai ,  Hung-Hsin Lin

IPC分类号： H01L2100

CPC分类号： H01L21/30604 ,  H01L21/3065 ,  H01L21/3083 ,  H01L27/1087

摘要： A method for removing black silicon in semiconductor fabrication is disclosed. First, a trench is formed in a semiconductor substrate having a pad dielectric layer and a hard mask layer. Then, the hard mask layer is removed. A photoresist layer covers the trench and only black silicon created at the edge of the semiconductor substrate during formation of the trench is left uncovered. Finally, the black silicon is removed.

摘要翻译： 公开了一种在半导体制造中去除黑硅的方法。 首先，在具有焊盘电介质层和硬掩模层的半导体衬底中形成沟槽。 然后，去除硬掩模层。 光致抗蚀剂层覆盖沟槽，并且在形成沟槽期间仅在半导体衬底的边缘处产生的黑色硅未被覆盖。 最后，黑硅被去除。

公开(公告)号：US06153482A

公开(公告)日：2000-11-28

申请号：US174091

申请日：1998-10-16

申请人： Lin-Chin Su ,  Tzu-Ching Tsai ,  Miin-Jiunn Jiang ,  Hung-Chang Liao ,  Jim Wang ,  Chung Min Lin

发明人： Lin-Chin Su ,  Tzu-Ching Tsai ,  Miin-Jiunn Jiang ,  Hung-Chang Liao ,  Jim Wang ,  Chung Min Lin

IPC分类号： H01L21/762 ,  H01L21/331 ,  H01L21/302 ,  H01L21/76

CPC分类号： H01L21/76205

摘要： A method for fabricating LOCOS isolation having a planar surface. The method utilizes a polysilicon spacer to prevent bird beak. The method adds the steps of forming a polishing stop layer and removing said edge-protrusion portion of the local oxide by chemical mechanical polishing.

摘要翻译： 一种用于制造具有平坦表面的LOCOS隔离的方法。 该方法利用多晶硅间隔物来防止鸟嘴。 该方法通过化学机械抛光添加形成抛光停止层并去除局部氧化物的边缘突出部分的步骤。

公开(公告)号：US08292635B2

公开(公告)日：2012-10-23

申请号：US13046708

申请日：2011-03-12

申请人： Terrance F. Little ,  Chia-Pin Liu ,  Ding-Cherng Chen ,  Tzu-Ching Tsai

发明人： Terrance F. Little ,  Chia-Pin Liu ,  Ding-Cherng Chen ,  Tzu-Ching Tsai

IPC分类号： H01R12/00

CPC分类号： H01R12/716 ,  H01R12/7029 ,  H01R12/73

摘要： A connector assembly (1000) includes a first connector (100) having a first insulative housing (11), a plurality of first terminals (12) supported by the first insulative housing and at least one latching member (13) combined with the first insulative housing, the latching member (13) having two locking arms (132) spaced apart from each other along a longitudinal direction; a second connector (200) having a second insulative housing (21), a plurality of second terminals (22) supported by the second insulative housing and at least one clasping member (23) combined with the second insulative housing, the clasping member (23) having a rigid longitudinal bar (232) with two free ends protruding at opposite directions; and wherein the rigid longitudinal bar is sandwiched between the two locking arms and the two free ends engaged with the two locking arms when the first connector mates with the second connector.

摘要翻译： 连接器组件（1000）包括具有第一绝缘壳体（11）的第一连接器（100），由第一绝缘壳体支撑的多个第一端子（12）和与第一绝缘壳体 所述闩锁构件（13）具有沿着纵向方向彼此间隔开的两个锁定臂（132）; 具有第二绝缘壳体（21）的第二连接器（200），由所述第二绝缘壳体支撑的多个第二端子（22）和与所述第二绝缘壳体组合的至少一个夹紧构件（23），所述夹紧构件 ）具有刚性纵向杆（232），两个自由端在相反方向突出; 并且其中当所述第一连接器与所述第二连接器配合时，所述刚性纵向杆夹在所述两个锁定臂之间并且所述两个自由端与所述两个锁定臂接合。

公开(公告)号：US08251723B2

公开(公告)日：2012-08-28

申请号：US12773027

申请日：2010-05-04

申请人： Tzu-Ching Tsai

发明人： Tzu-Ching Tsai

IPC分类号： H01R27/00

CPC分类号： H01R24/38 ,  H01R13/2421 ,  H01R2103/00

摘要： An electrical connector assembly includes a first connector and a second connector each defining a mating end of a regular polygon mating with each other. Each regular polygon defines a center, an imaginary circle around the center and a plurality of vertices at the imaginary circle. A plurality of pins are located at the mating ends which composed of one first pin at the center of the first connector, two second pins at least fulfilling with one half of the vertices and arranged at adjacent vertices in turn, one third pin at the center of the second connector and two forth pins at the vertices respectively in a condition that said two forth pins spaced from each other with a largest distance.

摘要翻译： 电连接器组件包括第一连接器和第二连接器，每个连接器和第二连接器限定彼此配合的正多边形的配合端。 每个正多边形定义中心，围绕中心的假想圆和在假想圆处的多个顶点。 多个销位于配合端，由第一连接器中心的一个第一销组成，两个第二销至少满足顶点的一半，依次布置在相邻的顶点处，中心位置为第三个销钉 的第二连接器和两个第四针在顶点处，分别处于所述两个第二引脚彼此间隔最大的条件下。

公开(公告)号：USD611419S1

公开(公告)日：2010-03-09

申请号：US29310952

申请日：2008-09-19

申请人： Tzu-Ching Tsai ,  Ren-Chih Li

设计人： Tzu-Ching Tsai ,  Ren-Chih Li

公开(公告)号：USD603797S1

公开(公告)日：2009-11-10

申请号：US29310951

申请日：2008-09-19

申请人： Tzu-Ching Tsai ,  Ren-Chih Li

设计人： Tzu-Ching Tsai ,  Ren-Chih Li

公开(公告)号：US20090053939A1

公开(公告)日：2009-02-26

申请号：US12229643

申请日：2008-08-25

申请人： Tzu-Ching Tsai

发明人： Tzu-Ching Tsai

IPC分类号： H01R13/10 ,  H01R13/02 ,  H01R24/00

CPC分类号： H01R12/716 ,  H01R12/57 ,  H01R13/115 ,  H01R13/41

摘要： An electrical connector mounted on a PCB (printed circuit board) includes an insulating housing having a receiving room and a plurality of contacts retained in the insulating housing. Said insulating housing has a tongue portion and a peripheral wall surrounds said tongue portion which defines said receiving room. Each contact includes a U-shaped contacting portion received in said receiving room, a vertical holding portion retained in an inner surface of said peripheral wall and a connecting portion connecting with said contacting portion and said holding portion. Said connecting portion has a linear leading surface which is formed slanted towards said contacting portion downwardly in order to provide a smooth mating process with a mating connector.

摘要翻译： 安装在PCB（印刷电路板）上的电连接器包括具有容纳室的绝缘壳体和保持在绝缘壳体中的多个触点。 所述绝缘壳体具有舌部和围绕限定所述接收室的所述舌部的周壁。 每个触点包括容纳在所述容纳室中的U形接触部分，保持在所述周壁的内表面中的垂直保持部分和与所述接触部分和所述保持部分连接的连接部分。 所述连接部分具有向下朝向所述接触部分倾斜地形成的线性前导表面，以便与配合连接器提供平滑的配合过程。