公开(公告)号：US08105900B2

公开(公告)日：2012-01-31

申请号：US12838495

申请日：2010-07-19

Applicant: Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: In a manufacturing method of a non-volatile memory, a substrate is provided, and strip-shaped isolation structures are formed in the substrate. A first memory array including memory cell columns is formed on the substrate. Each memory cell column includes memory cells connected in series with one another, a source/drain region disposed in the substrate outside the memory cells, select transistors disposed between the source/drain region and the memory cells, control gate lines extending across the memory cell columns and in a second direction, and first select gate lines respectively connecting the select transistors in the second direction in series. First contacts are formed on the substrate at a side of the first memory array and arranged along the second direction. Each first contact connects the source/drain regions in every two adjacent active regions.

Abstract translation: 在非易失性存储器的制造方法中，提供衬底，并且在衬底中形成条形隔离结构。 包括存储单元列的第一存储器阵列形成在衬底上。 每个存储单元列包括彼此串联连接的存储器单元，设置在存储单元外部的衬底中的源极/漏极区域，设置在源极/漏极区域和存储器单元之间的选择晶体管，跨越存储器单元延伸的控制栅极线 列和第二方向，并且首先选择分别连接第二方向上的选择晶体管的栅极线。 第一触点形成在第一存储器阵列的一侧的基板上，并沿第二方向布置。 每个第一接触件在每两个相邻有效区域中连接源极/漏极区域。

公开(公告)号：US07714445B2

公开(公告)日：2010-05-11

申请号：US11951274

申请日：2007-12-05

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

IPC: H01L23/552 ,  H01L21/768

CPC classification number: H01L27/0251 ,  H01L27/10894

Abstract: The invention provides a dynamic random access memory (DRAM) with an electrostatic discharge (ESD) region. The upper portion of the ESD plug is metal, and the lower portion of the ESD plug is polysilicon. This structure may improve the mechanical strength of the ESD region and enhance thermal conductivity from electrostatic discharging. In addition, the contact area between the ESD plugs and the substrate can be reduced without increasing aspect ratio of the ESD plugs. The described structure is completed by a low critical dimension controlled patterned photoresist, such that the processes and equipments are substantially maintained without changing by a wide margin.

Abstract translation: 本发明提供一种具有静电放电（ESD）区域的动态随机存取存储器（DRAM）。 ESD插头的上部是金属，ESD插头的下部是多晶硅。 该结构可以提高ESD区域的机械强度并增强静电放电的导热性。 此外，可以减少ESD插头和基板之间的接触面积，而不增加ESD插头的纵横比。 所描述的结构由低临界尺寸控制的图案化光致抗蚀剂完成，使得工艺和设备基本上保持而不会大幅变化。

公开(公告)号：US07642191B2

公开(公告)日：2010-01-05

申请号：US12019260

申请日：2008-01-24

Applicant: Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/311

CPC classification number: H01L21/823481 ,  H01L21/823437 ,  H01L27/115 ,  H01L27/11521

Abstract: A method of forming a semiconductor structure is provided. The method includes providing a substrate and forming a mask layer on the substrate, Next, dielectric isolations are formed in the mask layer and the substrate, wherein the dielectric isolations extend above the substrate. Then, the mask layer is removed to expose a portion of the substrate, and a dielectric layer is formed on the exposed portion of the substrate. Subsequently, a first conductive layer is formed on the dielectric layer, and a portion of the dielectric isolation is removed, wherein a top surface of the remaining dielectric isolation is lower than a top surface of the first conductive layer. Moreover, a conformal layer is formed over the substrate, and a second conductive layer is formed on the conformal layer.

Abstract translation: 提供一种形成半导体结构的方法。 该方法包括提供衬底并在衬底上形成掩模层。接下来，在掩模层和衬底中形成介电隔离，其中介电隔离物延伸到衬底上方。 然后，去除掩模层以露出衬底的一部分，并且在衬底的暴露部分上形成电介质层。 随后，在电介质层上形成第一导电层，去除介电隔离的一部分，其中绝缘隔离的顶表面低于第一导电层的顶表面。 此外，在衬底上形成保形层，并且在保形层上形成第二导电层。

公开(公告)号：US20090087975A1

公开(公告)日：2009-04-02

申请号：US12018209

申请日：2008-01-23

Applicant: Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/3205

CPC classification number: H01L27/11521

Abstract: A method for manufacturing a memory includes first providing a substrate with a horizontally adjacent control gate region and floating gate region which includes a sacrificial layer and sacrificial sidewalls, removing the sacrificial layer and sacrificial sidewalls to expose the substrate, forming dielectric sidewalls adjacent to the control gate region, forming a floating gate dielectric layer on the exposed substrate and forming a floating gate layer adjacent to the dielectric sidewalls and on the floating gate dielectric layer.

Abstract translation: 一种用于制造存储器的方法，包括首先提供具有水平相邻的控制栅极区域和浮置栅极区域的衬底，该栅极区域包括牺牲层和牺牲侧壁，去除牺牲层和牺牲侧壁以露出衬底，形成邻近控制的电介质侧壁 栅极区域，在暴露的衬底上形成浮栅电介质层，并形成与电介质侧壁相邻的浮栅极和浮置栅极电介质层。

公开(公告)号：US20090087544A1

公开(公告)日：2009-04-02

申请号：US12039744

申请日：2008-02-29

Applicant: Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: B05D5/12

CPC classification number: H01L29/7923 ,  H01L27/115 ,  H01L27/11568

Abstract: The memory cell of the present invention has two independent storage regions embedded into two opposite sidewalls of the control gate respectively. In this way, the data storage can be more reliable. Other features of the present invention are that the thickness of the dielectric layers is different, and the two independent storage regions are formed on opposite bottom sides of the opening by the etching process and form a shape like a spacer. The advantage of the aforementioned method is that the fabricating process is simplified and the difficulty of self-alignment is reduced.

Abstract translation: 本发明的存储单元具有分别嵌入控制门的两个相对的侧壁中的两个独立的存储区域。 以这种方式，数据存储可以更可靠。 本发明的其他特征是电介质层的厚度不同，并且两个独立的存储区域通过蚀刻工艺形成在开口的相对的底侧上并形成像间隔物的形状。 上述方法的优点是简化了制造工艺，并且减少了自对准的难度。

公开(公告)号：US20090065846A1

公开(公告)日：2009-03-12

申请号：US11955396

申请日：2007-12-13

Applicant: Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7887

Abstract: A manufacturing method of a non-volatile memory includes forming a first dielectric layer, a first conductive layer, and a first cap layer sequentially on a substrate to form first gate structures; conformally forming a second dielectric layer on the substrate; forming a first spacer having a larger wet etching rate than the second dielectric layer on each sidewall of each first gate structure; partially removing the first and second dielectric layers to expose the substrate. A third dielectric layer is formed on the substrate between the first gate structures; removing the first spacer; forming a second conductive layer on the third dielectric layer; removing the first cap layer and a portion of the first conductive layer to form second gate structures; and forming doped regions in the substrate at two sides of each second gate structure.

Abstract translation: 非易失性存储器的制造方法包括在衬底上依次形成第一电介质层，第一导电层和第一覆盖层，以形成第一栅极结构; 在基底上保形地形成第二电介质层; 在每个第一栅极结构的每个侧壁上形成具有比第二介电层更大的湿蚀刻速率的第一间隔物; 部分地去除第一和第二电介质层以暴露衬底。 在第一栅极结构之间的衬底上形成第三电介质层; 去除第一间隔物; 在所述第三介电层上形成第二导电层; 移除所述第一盖层和所述第一导电层的一部分以形成第二栅极结构; 以及在每个第二栅极结构的两侧在衬底中形成掺杂区域。

公开(公告)号：US20080315284A1

公开(公告)日：2008-12-25

申请号：US11953886

申请日：2007-12-11

Applicant: Ching-Nan Hsiao ,  Chung-Lin Huang ,  Chen-Yu Tsai ,  Chung-Yuan Lee

Inventor： Ching-Nan Hsiao ,  Chung-Lin Huang ,  Chen-Yu Tsai ,  Chung-Yuan Lee

IPC: H01L29/00 ,  H01L21/336

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11543

Abstract: A flash memory cell includes a substrate, a T-shaped control gate disposed above the substrate, a floating gate embedded in a lower recess of the T-shaped control gate, a dielectric layer between the T-shaped control gate and the floating gate; a cap layer above the T-shaped control gate, a control gate oxide between the T-shaped control gate and the substrate, a floating gate oxide between the floating gate and the substrate, a liner covering the cap layer and the floating gate, and a source/drain region adjacent to the floating gate. The floating gate has a vertical wall surface that is coplanar with one side of the dielectric layer.

Abstract translation: 闪存单元包括衬底，设置在衬底上方的T形控制栅极，嵌入在T形控制栅极的下凹槽中的浮置栅极，在T形控制栅极和浮置栅极之间的介电层; T形控制栅极上方的覆盖层，T形控制栅极和衬底之间的控制栅极氧化物，浮置栅极和衬底之间的浮置栅极氧化物，覆盖覆盖层和浮动栅极的衬底，以及 与浮动栅极相邻的源极/漏极区域。 浮动栅极具有与电介质层的一侧共面的垂直壁表面。

公开(公告)号：US20080296725A1

公开(公告)日：2008-12-04

申请号：US11955399

申请日：2007-12-13

Applicant: Ching-Nan Hsiao ,  Chung-Lin Huang ,  Chen-Yu Tsai ,  Chung-Yuan Lee

Inventor： Ching-Nan Hsiao ,  Chung-Lin Huang ,  Chen-Yu Tsai ,  Chung-Yuan Lee

IPC: H01L23/00 ,  H01L21/76

CPC classification number: H01L21/823481 ,  H01L27/11521

Abstract: A semiconductor component includes a substrate, two isolation structures, a conductor pattern and a dielectric layer. The isolation structures are disposed in the substrate, and each of the isolation structures has protruding portions protruding from the surface of the substrate. A trench is formed between the protruding portions. The included angle formed by the sidewall of the protruding portion and the surface of the substrate is an obtuse angle. The conductor pattern is disposed in the trench and fills the trench up. The dielectric layer is disposed between the conductor pattern and the substrate.

Abstract translation: 半导体部件包括基板，两个隔离结构，导体图案和电介质层。 隔离结构设置在基板中，并且每个隔离结构具有从基板的表面突出的突出部分。 在突出部之间形成沟槽。 由突出部分的侧壁和基板的表面形成的夹角是钝角。 导体图案设置在沟槽中并将沟槽填满。 电介质层设置在导体图案和基板之间。

公开(公告)号：US06855966B2

公开(公告)日：2005-02-15

申请号：US10435416

申请日：2003-05-09

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang

IPC: H01L21/8247 ,  H01L27/115 ,  H01L31/072 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/109

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521

Abstract: A floating gate and a fabricating method of the same. A semiconductor substrate is provided. A gate dielectric layer and a conducting layer are sequentially formed on the semiconductor substrate. A patterned hard mask layer having an opening is formed on the conducting layer, wherein a portion of the conducting layer is exposed through the opening. A spacer is formed on the sidewall of the opening. The patterned hard mask layer is removed. A conducting spacer is formed on the sidewall of the spacer. The exposed conducting layer and the exposed gate dielectric layer are sequentially removed.

Abstract translation: 浮栅及其制造方法。 提供半导体衬底。 在半导体衬底上依次形成栅介电层和导电层。 在导电层上形成具有开口的图案化的硬掩模层，其中导电层的一部分通过开口露出。 间隔件形成在开口的侧壁上。 图案化的硬掩模层被去除。 导电间隔件形成在间隔件的侧壁上。 依次去除暴露的导电层和暴露的栅介质层。

公开(公告)号：US06770520B2

公开(公告)日：2004-08-03

申请号：US10436800

申请日：2003-05-13

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L21337

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which a gate dielectric layer, a conducting layer, and a patterned hard mask layer are sequentially formed. The surface of the conducting layer is covered by the patterned hard mask layer to form a gate. The conducting layer is etched to a predetermined depth to form an indentation using the patterned hard mask layer as a mask. The conducting layer is oxidized to form an oxide layer on the surface of the conducting layer. The oxide layer and the conducting layer are etched to form multiple tips using the patterned hard mask layer as a mask.

Abstract translation: 浮栅及其制造方法。 提供半导体衬底，其上依次形成栅介电层，导电层和图案化的硬掩模层。 导电层的表面被图案化的硬掩模层覆盖以形成栅极。 使用图案化的硬掩模层作为掩模，将导电层蚀刻到预定深度以形成凹陷。 导电层被氧化以在导电层的表面上形成氧化物层。 使用图案化的硬掩模层作为掩模，蚀刻氧化物层和导电层以形成多个尖端。