公开(公告)号：US11825648B2

公开(公告)日：2023-11-21

申请号：US17323863

申请日：2021-05-18

Applicant: United Microelectronics Corp.

Inventor： Kuo-Hsing Lee ,  Chi-Horn Pai ,  Chang Chien Wong ,  Sheng-Yuan Hsueh ,  Ching Hsiang Tseng ,  Shih-Chieh Hsu

IPC: H10B20/20

CPC classification number: H10B20/20

Abstract: A one-time programmable memory structure including a substrate, a transistor, a capacitor, and an interconnect structure is provided. The transistor is located on the substrate. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is disposed above the substrate. The second electrode is disposed on the first electrode. The first electrode is located between the second electrode and the substrate. The insulating layer is disposed between the first electrode and the second electrode. The interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode.

公开(公告)号：US20230317715A1

公开(公告)日：2023-10-05

申请号：US17732570

申请日：2022-04-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chih-Kai Kang ,  Chun-Hsien Lin ,  Chi-Horn Pai

IPC: H01L27/06 ,  H01L29/78 ,  H01L29/94 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L29/7851 ,  H01L29/66181 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/94

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.

公开(公告)号：US11631761B2

公开(公告)日：2023-04-18

申请号：US17676867

申请日：2022-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Chih-Kai Kang ,  Guan-Kai Huang ,  Chien-Liang Wu

IPC: H01L29/778 ,  H01L29/66

Abstract: A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).

公开(公告)号：US20230015480A1

公开(公告)日：2023-01-19

申请号：US17391067

申请日：2021-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chun-Hsien Lin ,  Yung-Chen Chiu ,  Chien-Liang Wu ,  Te-Wei Yeh

IPC: H01L27/112

Abstract: A one-time programmable (OTP) memory cell includes a substrate having a first conductivity type and having an active area surrounded by an isolation region, a transistor disposed on the active area, and a capacitor disposed on the active area and electrically coupled to the transistor. The capacitor comprises a diffusion region of a second conductivity type in the substrate, a metallic film in direct contact with the active area, a capacitor dielectric layer on the metallic film, and a metal gate surrounded by the capacitor dielectric layer. The diffusion region and the metallic film constitute a capacitor bottom plate.

公开(公告)号：US20220302118A1

公开(公告)日：2022-09-22

申请号：US17230975

申请日：2021-04-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Kun-Hsien Lee ,  Sheng-Yuan Hsueh ,  Chang-Chien Wong ,  Ching-Hsiang Tseng ,  Tsung-Hsun Wu ,  Chi-Horn Pai ,  Shih-Chieh Hsu

IPC: H01L27/108

Abstract: The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.

公开(公告)号：US11296036B2

公开(公告)日：2022-04-05

申请号：US16986270

申请日：2020-08-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Kang ,  Sheng-Yuan Hsueh ,  Yi-Chung Sheng ,  Kuo-Yu Liao ,  Shu-Hung Yu ,  Hung-Hsu Lin ,  Hsiang-Hung Peng

IPC: H01L23/544 ,  H01L27/092 ,  H01L27/02 ,  G03F9/00 ,  H01L21/8238

Abstract: A mark pattern includes unit cells immediately adjacent to each other and arranged in a form of dot matrix to form a register mark or an identification code, wherein each unit cell has configuration identical to functional devices of pMOS and nMOS, and each unit cell includes a first active region, a second active region isolated from the first active region, and first gate structures extending along a first direction and are arranged along a second direction perpendicular to the first direction, and the first gate structures straddling the first active region and the second active region, contact structures disposed between the first gate structures on the first active region and the second active region, and via structures disposed on the contact structures and two opposite ends of the first gate structures.

公开(公告)号：US20220093584A1

公开(公告)日：2022-03-24

申请号：US17075707

申请日：2020-10-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chien-Liang Wu ,  Te-Wei Yeh ,  Yi-Chun Chen

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L21/306 ,  H01L21/765 ,  H01L21/8252

Abstract: A resistor-transistor-logic (RTL) circuit with GaN structure, including a GaN layer, a AlGaN barrier layer on the GaN layer, multiple p-type doped GaN capping layers on the AlGaN barrier layer, wherein parts of the p-type doped GaN capping layers in a high-voltage region and in a low-voltage region convert the underlying GaN layer into gate depletion areas, the GaN layer not covered by the p-type doped GaN capping layers in a resistor region becomes a 2DEG resistor.

公开(公告)号：US20220059528A1

公开(公告)日：2022-02-24

申请号：US17516721

申请日：2021-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Chen Chiu ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chien-Liang Wu ,  Chih-Kai Kang ,  Guan-Kai Huang

IPC: H01L27/06 ,  H01L27/085 ,  H01L29/66 ,  H01L29/778

Abstract: A 3D semiconductor structure includes a buffer layer, a n-type high electron mobility transistor (HEMT) disposed on a first surface of the buffer layer, and a p-type high hole mobility transistor (HHMT) disposed on a second surface of the buffer layer opposite to the first surface.

公开(公告)号：US20210391383A1

公开(公告)日：2021-12-16

申请号：US16924169

申请日：2020-07-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Te-Wei Yeh ,  Chien-Liang Wu

IPC: H01L27/22 ,  H01L43/02 ,  G11C7/18

Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).

公开(公告)号：US20210210550A1

公开(公告)日：2021-07-08

申请号：US17207728

申请日：2021-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ting-Hsiang Huang ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chih-Kai Kang

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle, a top view of the first metal interconnection includes a flat oval overlapping the circle, and the MTJ includes a bottom electrode, a fixed layer, a free layer, a capping layer, and a top electrode.