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公开(公告)号：US12300701B2
公开(公告)日：2025-05-13
申请号：US17621257
申请日：2021-12-09
Inventor： Fei Ai , Dewei Song , Chengzhi Luo
IPC: H01L27/12 , G02F1/1362
Abstract: An array substrate and a display panel are provided. The array substrate includes a substrate, an array layer, an inorganic insulation layer, a conductive electrode, a passivation layer, and a pixel electrode disposed in sequence. The array layer includes a source electrode and a drain electrode. A first via hole is defined in the array substrate. The first via hole penetrates the passivation layer and the inorganic insulation layer and exposes the drain electrode. The pixel electrode is connected to the drain electrode in the first via hole.
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公开(公告)号：US12276888B2
公开(公告)日：2025-04-15
申请号：US17776384
申请日：2022-04-13
Inventor： Fan Gong , Guanghui Liu , Fei Ai , Jiyue Song , Dewei Song , Rui He
IPC: G02F1/1362 , G02F1/1335 , G02F1/135 , G02F1/1368
Abstract: Embodiments of the present disclosure provide a display panel and a display terminal. The display panel includes at least one ultraviolet sensing transistor and at least one control transistor disposed on a substrate, and a color film substrate including a light blocking unit; wherein the ultraviolet sensing transistor includes an ultraviolet absorbing layer, and an orthographic projection of the light blocking unit on the substrate covers an orthographic projection of the ultraviolet absorbing layer on the substrate. According to the embodiment of the present disclosure, the light blocking unit absorbs or blocks the visible lights to prevent the visible lights from entering into the ultraviolet absorbing layer.
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公开(公告)号：US12165609B2
公开(公告)日：2024-12-10
申请号：US17613579
申请日：2021-09-06
Inventor： Haiming Cao , Chao Tian , Yanqing Guan , Fei Ai , Guanghui Liu , Zhifu Li
IPC: G09G3/36
Abstract: The present application provides a display panel in which transistors in an input pull-up module, a stage transfer output module, and an output pull-up module are provided as P-type low temperature polysilicon thin film transistors, and a transistor in an output pull-down module is provided as an N-type metal oxide thin film transistor.
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公开(公告)号：US12094888B2
公开(公告)日：2024-09-17
申请号：US17278722
申请日：2021-02-05
Inventor： Tao Ma , Yong Xu , Wanglin Wen , Fei Ai
IPC: H01L27/12 , H01L29/786
CPC classification number: H01L27/1244 , H01L27/1222 , H01L27/1288 , H01L29/78675
Abstract: An array substrate includes a substrate, a first metal layer and an active layer disposed on the substrate, an interlayer insulating layer, and a second metal layer. The first metal layer forms at least one first trace, the interlayer insulating layer is disposed on the first metal layer and the active layer, the second metal layer is disposed on the interlayer insulating layer, the interlayer insulating layer is formed with a first contact hole, and the second metal layer is connected to the first trace through the first contact hole. The first metal layer includes a conductive layer and a first protective layer stacked in sequence.
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公开(公告)号：US12087080B2
公开(公告)日：2024-09-10
申请号：US17419621
申请日：2021-05-24
Inventor： Wanglin Wen , Fei Ai , Yong Xu
IPC: G06V40/13 , H01L25/16 , H01L27/146
CPC classification number: G06V40/1318 , G06V40/1306 , H01L25/167 , H01L27/14636 , H01L27/14643
Abstract: A display panel and a manufacturing method thereof are provided. A fingerprint recognition module and a storage capacitor of the display panel are disposed in a thin-film transistor (TFT) device layer. The fingerprint recognition module is electrically connected to an active layer and the storage capacitor of a TFT by an electrode layer, thereby optimizing a structure of an array substrate. Furthermore, the display panel can better receive reflected light signals and has improved fingerprint recognition performance. The display panel has a simple manufacturing process and low manufacturing costs.
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Patent Agency Ranking
公开(公告)号：US12068330B2
公开(公告)日：2024-08-20
申请号：US16966116
申请日：2020-01-17
Inventor： Yuan Yan , Yong Xu , Fei Ai , Dewei Song
CPC classification number: H01L27/124 , G06F3/041 , G06F3/0412 , G06F3/04164 , G06F3/0443 , H01L27/1288 , G06F2203/04103
Abstract: A touch array substrate and a manufacturing method thereof, wherein in the touch array substrate, an active layer, an insulating layer, a pixel electrode layer, a metal layer, a planarization layer, and a common electrode layer are sequentially disposed on the buffer layer. The active layer includes a first region corresponding to a source electrode and a second region corresponding to a drain electrode. The pixel electrode layer includes a plurality of base layers. The metal layer is correspondingly disposed on the base layers. The metal layer includes a touch signal line, a data line, and a gate electrode. The common electrode layer includes a touch electrode, the source electrode, and the drain electrode.
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公开(公告)号：US12046172B2
公开(公告)日：2024-07-23
申请号：US17434790
申请日：2021-07-15
Inventor： Mingyue Li , Chao Tian , Yanqing Guan , Fei Ai , Guanghui Liu
IPC: G09G3/20
CPC classification number: G09G3/20 , G09G2310/0267 , G09G2310/0283
Abstract: The present application discloses a gate drive circuit and a display device. The gate drive circuit includes a plurality of cascaded gate drive units, in which one of the gate drive units includes a first layout, an input module and a pull-up module. By receiving a potential changeable signal by the gate of a first transistor or the gate of a second thin-film transistor, it can alleviate or avoid current leakage caused when a first node keeps at a same voltage level for a long time, thereby improving the stability of the potential of the first node.
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公开(公告)号：US20240222446A1
公开(公告)日：2024-07-04
申请号：US17996787
申请日：2022-08-30
Inventor： Fei Ai , Dewei Song
IPC: H01L29/417 , H01L29/08 , H01L29/49 , H01L29/66 , H01L29/786
CPC classification number: H01L29/41733 , H01L29/0847 , H01L29/4908 , H01L29/66757 , H01L29/66969 , H01L29/78675 , H01L29/7869
Abstract: The present application provides a thin film transistor and an electronic device. The thin film transistor includes: a crystalline active pattern, wherein the crystalline active pattern includes a channel and two contact portions, and the two contact portions are connected to opposite two sides of the channel in a direction intersecting a thickness direction of the crystalline active pattern; a groove located on at least one of the two contact portions and extending in the thickness direction of the crystalline active pattern; a source electrode and a drain electrode connected to the two contact portions, respectively; and an insulating layer being in contact with the channel.
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公开(公告)号：US20240027859A1
公开(公告)日：2024-01-25
申请号：US17607852
申请日：2021-09-08
Inventor： Zhilin Wu , Tao Ma , Dewei Song , Fei Ai
IPC: G02F1/1362 , G02F1/1343 , G02F1/1333 , G02F1/1368
CPC classification number: G02F1/136295 , G02F1/136209 , G02F1/1343 , G02F1/136227 , G02F1/13338 , G02F1/1368
Abstract: The present application discloses a display panel and an electrical terminal. The display panel includes: an underlay; an array driver layer located on the underlay and including a gate electrode layer and a source and drain electrode layer; a signal line including an adaptor portion located in the non-display region, wherein the adaptor portion includes a first wire section disposed in a same layer with the gate electrode layer, a second wire section disposed in a same layer with the source and drain electrode layer, and a bridge portion electrically connected to the first wire section and the second wire section; wherein the first wire section, the second wire section, and the bridge portion are disposed in different layers.
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公开(公告)号：US11796847B2
公开(公告)日：2023-10-24
申请号：US17600321
申请日：2021-08-19
IPC: G02F1/1333 , G02F1/1362 , G02F1/1343 , H01L27/12 , H01L29/786 , H01L29/66
CPC classification number: G02F1/133345 , G02F1/133357 , G02F1/134309 , G02F1/136204 , H01L27/1222 , H01L27/1274 , H01L29/66757 , H01L29/78675 , G02F2201/07
Abstract: An array substrate, includes: a substrate, a first metal layer, a first buffer layer, and an active layer, a gate insulating layer, a second metal layer, a first insulating layer, a third metal layer and a first planarization layer. The first metal layer is electrically connected with the first doped area of the active layer through the bridge layer of the second metal layer. The third metal layer is electrically connected with the second doped area of the active layer. The array substrate of the present disclosure reduces a size of a thin film transistor by stacking the first metal layer, the second metal layer, and the third metal layer, thereby increasing pixel density. A display panel is also provided.
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