公开(公告)号：US08686789B2

公开(公告)日：2014-04-01

申请号：US13329699

申请日：2011-12-19

申请人： Xicheng Jiang ,  Minsheng Wang

发明人： Xicheng Jiang ,  Minsheng Wang

IPC分类号： H03F3/38

CPC分类号： H03F1/305 ,  H03F3/217 ,  H03G3/348

摘要： A Class-D amplifier arrangement is disclosed that implements an auxiliary feedback loop and a primary feedback loop. The auxiliary feedback loop operates upon an input signal when the Class-D amplifier arrangement is operating under a power-up condition and a power-down condition so that a modulated signal is confined within the auxiliary feedback loop during the power-up condition and the power-down condition. The confinement of the modulated signal within the auxiliary feedback loop during the power-up condition and the power-down condition diverts transient signals coupled onto the modulated signal from an output device. The primary feedback loop operates upon the input signal when the Class-D amplifier arrangement is operating under a normal condition so that the modulated signal is introduced to the output device during the normal condition.

摘要翻译： 公开了一种实现辅助反馈回路和主反馈回路的D类放大器装置。 当D类放大器装置在上电条件和掉电条件下工作时，辅助反馈回路根据输入信号工作，使得在上电条件期间调制信号被限制在辅助反馈回路内， 断电状态。 在上电状态和掉电状态期间，辅助反馈环路内的调制信号的限制将耦合到来自输出设备的调制信号的瞬态信号转移。 当D类放大器装置在正常条件下工作时，主反馈环路根据输入信号进行工作，使得在正常状态期间将调制信号引入输出装置。

公开(公告)号：US20130154736A1

公开(公告)日：2013-06-20

申请号：US13329699

申请日：2011-12-19

申请人： Xicheng JIANG ,  Minsheng Wang

发明人： Xicheng JIANG ,  Minsheng Wang

IPC分类号： H03F3/217

CPC分类号： H03F1/305 ,  H03F3/217 ,  H03G3/348

摘要： A Class-D amplifier arrangement is disclosed that implements an auxiliary feedback loop and a primary feedback loop. The auxiliary feedback loop operates upon an input signal when the Class-D amplifier arrangement is operating under a power-up condition and a power-down condition so that a modulated signal is confined within the auxiliary feedback loop during the power-up condition and the power-down condition. The confinement of the modulated signal within the auxiliary feedback loop during the power-up condition and the power-down condition diverts transient signals coupled onto the modulated signal from an output device. The primary feedback loop operates upon the input signal when the Class-D amplifier arrangement is operating under a normal condition so that the modulated signal is introduced to the output device during the normal condition.

摘要翻译： 公开了一种实现辅助反馈回路和主反馈回路的D类放大器装置。 当D类放大器装置在上电条件和掉电条件下工作时，辅助反馈回路根据输入信号工作，使得在上电条件期间调制信号被限制在辅助反馈回路内， 断电状态。 在上电状态和掉电状态期间，辅助反馈环路内的调制信号的限制将耦合到来自输出设备的调制信号的瞬态信号转移。 当D类放大器装置在正常条件下工作时，主反馈环路根据输入信号进行工作，使得在正常状态期间将调制信号引入输出装置。

公开(公告)号：US08237496B2

公开(公告)日：2012-08-07

申请号：US12804834

申请日：2010-07-29

申请人： Xicheng Jiang ,  Jungwoo Song ,  Minsheng Wang ,  Todd L. Brooks

发明人： Xicheng Jiang ,  Jungwoo Song ,  Minsheng Wang ,  Todd L. Brooks

IPC分类号： H03F3/38

CPC分类号： H03F3/217

摘要： Disclosed is a switching amplifier having an enhanced supply rejection. The switching amplifier comprises a digital modulator that provides a modulated signal. The switching amplifier further comprises a closed-loop analog driver that is coupled to the digital modulator. As disclosed, the closed-loop analog driver is configured to re-modulate a modulation signal that corresponds to the modulated signal. An output stage of the switching amplifier is driven by the re-modulated signal, thereby providing enhanced supply rejection. In one embodiment, the modulated signal is produced by a digital pulse-width modulator (PWM) circuit of a Class-D amplifier, and has a pulse rate substantially less than a clock rate of the digital PWM circuit. In one embodiment, the switching amplifier is implemented as an audio amplifier in a mobile communication device such as a cellular telephone.

摘要翻译： 公开了具有增强的电源抑制的开关放大器。 开关放大器包括提供调制信号的数字调制器。 开关放大器还包括耦合到数字调制器的闭环模拟驱动器。 如所公开的，闭环模拟驱动器被配置为重新调制对应于调制信号的调制信号。 开关放大器的输出级由再调制信号驱动，从而提供增强的电源抑制。 在一个实施例中，调制信号由D类放大器的数字脉冲宽度调制器（PWM）电路产生，并且具有基本上小于数字PWM电路的时钟速率的脉冲速率。 在一个实施例中，开关放大器被实现为诸如蜂窝电话的移动通信设备中的音频放大器。

公开(公告)号：US07653204B2

公开(公告)日：2010-01-26

申请号：US10926762

申请日：2004-08-26

申请人： Yue Chen ,  Nelson Sollenberger ,  Minsheng Wang

发明人： Yue Chen ,  Nelson Sollenberger ,  Minsheng Wang

IPC分类号： H04B1/00

CPC分类号： G10H7/004 ,  G10H2230/021 ,  G10H2250/631

摘要： In an audio processing device, a method and system for improved CODEC with polyringer are provided. An audio CODEC may comprise an audio ADC, an audio DAC, and a sidetone generator. Data from an external microphone may be processed by an audio ADC and may be sent to a processor that may be adapted to perform digital signal processing operations. The audio DAC may receive from the processor digital audio and polyphonic ringer data and may process the digital audio and polyphonic ringer data through separate digital filters and digital interpolators. The audio DAC may add the processed digital audio and polyphonic ringer data before analog conversion. The audio DAC may perform analog conversion by utilizing a delta-sigma modulator, a current-based DAC, and a switched-capacitor filter. The converted data may be filtered with an RC filter and may be utilized to drive an external speaker or earpiece.

摘要翻译： 在一种音频处理装置中，提供了一种用于改进具有多声道的CODER的方法和系统。 音频CODEC可以包括音频ADC，音频DAC和侧音发生器。 来自外部麦克风的数据可以由音频ADC处理，并且可以被发送到可适于执行数字信号处理操作的处理器。 音频DAC可以从处理器接收数字音频和复音振铃器数据，并且可以通过单独的数字滤波器和数字内插器处理数字音频和复音振铃器数据。 音频DAC可以在模拟转换之前添加经处理的数字音频和复音振铃器数据。 音频DAC可以通过利用Δ-Σ调制器，基于电流的DAC和开关电容滤波器来执行模拟转换。 转换的数据可以用RC滤波器滤波，并且可以用于驱动外部扬声器或听筒。

公开(公告)号：US07609110B2

公开(公告)日：2009-10-27

申请号：US11797037

申请日：2007-04-30

申请人： Minsheng Wang

发明人： Minsheng Wang

IPC分类号： H03F3/38

CPC分类号： H03F3/2173 ,  H03F1/0205 ,  H03F3/217 ,  H03F2200/03 ,  H03F2200/351 ,  H03F2200/384

摘要： Methods for designing a filterless class-D amplifier and driver are described herein. In the exemplary embodiment, a feedback loop is used to stabilize the filterless class-D amplifier. A pulse width modulated (PWM) output signal is generated by adding a comparator input signal to a comparative signal, and comparing the sum to a peak voltage, which can be a peak value of the comparative signal. A limit of one PWM sample will be generated half per period of the comparative signal, resulting in lower dynamic switching noise and a decreased sensitivity to jitter noise than conventional filterless class-D amplifiers.

摘要翻译： 本文描述了设计无滤波D类放大器和驱动器的方法。 在示例性实施例中，使用反馈环来稳定无滤波D类放大器。 通过将比较器输入信号与比较信号相加，并将该和与峰值电压进行比较，产生脉冲宽度调制（PWM）输出信号，峰值电压可以是比较信号的峰值。 一个PWM采样的限制将在比较信号的每个周期产生一半，导致比传统的无滤波D类放大器更低的动态开关噪声和对抖动噪声的灵敏度降低。

公开(公告)号：US07010557B2

公开(公告)日：2006-03-07

申请号：US10106549

申请日：2002-03-27

申请人： Minsheng Wang

发明人： Minsheng Wang

IPC分类号： G06F17/17

CPC分类号： H03H17/0279 ,  H03H17/0664 ,  H03H17/0671

摘要： A decimation system comprising a plurality, L, of cascaded Finite Impulse Response (FIR) decimation filters. Each decimation filter has a transfer function of the form H(z)=(1+z−1)N, where N is an integer. Each FIR decimation filter performs decimation by a common factor I. The cascaded FIR decimation filters together achieve a decimation result substantially identical to that of an Nth-order CIC filter (that is, a CIC filter having N integrator stages) that performs decimation by a factor IL.

摘要翻译： 一种抽取系统，包括多个级联的有限脉冲响应（FIR）抽取滤波器。 每个抽取滤波器具有形式为H（z）=（1 + z 0 - 1）的传递函数，其中N是整数。 每个FIR抽取滤波器通过公共因子I执行抽取。级联FIR抽取滤波器一起实现与第N个次级CIC滤波器（即，具有N个N个CIC滤波器的CIC滤波器）基本相同的抽取结果 积分器级），其通过因子I ^{L执行抽取。}

公开(公告)号：US20050179574A1

公开(公告)日：2005-08-18

申请号：US11031071

申请日：2005-01-10

申请人： Minsheng Wang ,  Jungwoo Song

发明人： Minsheng Wang ,  Jungwoo Song

IPC分类号： H03M3/00 ,  H03M7/32

CPC分类号： H03M7/3042

摘要： Provided are a system and method for implementing a multirate analog finite impulse response (FIR) filter. A system of the present invention includes a modulator having a first adder and a quantizer. The first adder includes an output port, and the quantizer includes (i) an input port coupled to the first adder output port and (ii) a quantizer output port. A second adder is also included, having one input port coupled to the first adder output port and another input port coupled to the quantizer output port. Also included are at least two two-unit delays, a first of the two-unit delays having an input port coupled to an output port of the second adder, and an output port coupled to an input port of the second of the two-unit delays. An output port of the second two-unit delays is coupled to a first input port of the first adder.

摘要翻译： 提供了一种用于实现多速率模拟有限脉冲响应（FIR）滤波器的系统和方法。 本发明的系统包括具有第一加法器和量化器的调制器。 第一加法器包括输出端口，并且量化器包括（i）耦合到第一加法器输出端口的输入端口和（ii）量化器输出端口。 还包括第二加法器，具有耦合到第一加法器输出端口的一个输入端口和耦合到量化器输出端口的另一个输入端口。 还包括至少两个两单元延迟，两单元延迟中的第一个具有耦合到第二加法器的输出端口的输入端口，以及耦合到两单元中的第二个单元的输入端口的输出端口 延误 第二两单元延迟的输出端口耦合到第一加法器的第一输入端口。

公开(公告)号：US06864819B2

公开(公告)日：2005-03-08

申请号：US10784934

申请日：2004-02-25

申请人： Minsheng Wang

发明人： Minsheng Wang

IPC分类号： H03H17/02 ,  H03M1/06 ,  H03M1/66 ,  H03M7/36 ,  H03M3/00

CPC分类号： H03M1/066 ,  H03H17/02 ,  H03H17/0261 ,  H03M1/66 ,  H03M3/502

摘要： A filter structure used with a dynamic element matching encoder for a sigma-delta digital-to-analog converter is presented. A sampled input sequence having undesired frequency tones is divided into even and odd data sub-sequences. Each of the sub-sequences is processed by a dynamic element matching encoder, with a transfer function H(z−1). The resulting processed sub-sequences are combined into an output sequence. The undesired frequency tones are substantially reduced in the output sequence.

摘要翻译： 提出了一种与Σ-Δ数模转换器的动态元件匹配编码器一起使用的滤波器结构。 具有不期望的频率音调的采样输入序列被划分为偶数和奇数数据子序列。 每个子序列由具有传递函数H（z -1）的动态元素匹配编码器处理。 所得到的经处理的子序列被组合成输出序列。 在输出序列中，不期望的频率音调显着降低。