-
公开(公告)号：US20240064978A1
公开(公告)日：2024-02-22
申请号：US17891055
申请日：2022-08-18
发明人： Jingtao Xie , Bingjie Yan , Kun Zhang , Wenxi Zhou , Zhiliang Xia , Zongliang Huo
IPC分类号： H01L27/11582 , H01L27/11556
CPC分类号： H01L27/11582 , H01L27/11556
摘要： A three-dimensional (3D) memory device includes a stack, a plurality of contact structures, and a plurality of support structures. The stack in an insulating structure includes a plurality of conductive layers and a plurality of dielectric layers stacked alternatingly, and the stack includes a staircase structure. The plurality of contact structures each extends through the insulating structure and in contact with a respective conductive layer of the plurality of conductive layers in the staircase structure. The plurality of support structures extends through the stack in the staircase structure. Each support structure is in contact with one of the plurality of contact structures.
-
公开(公告)号：US11871567B2
公开(公告)日：2024-01-09
申请号：US17212754
申请日：2021-03-25
发明人： Kun Zhang
IPC分类号： H01L27/11582 , H01L27/11519 , H10B43/27 , H10B41/10 , H10B41/27 , H10B43/10 , H10B41/35 , H10B43/35
摘要： A three-dimensional (3D) memory device is disclosed. The 3D memory device comprises an alternating layer stack on a substrate, and a top selective gate cut structure having a laminated structure embedded in an upper portion of the alternating layer stack and extending along a lateral direction. The laminated structure of the top selective gate cut structure comprises a dielectric filling wall and a dummy channel and a dummy functional layer on both sides of the dielectric filling wall.
-
公开(公告)号：US20230354577A1
公开(公告)日：2023-11-02
申请号：US17731520
申请日：2022-04-28
发明人： Dongxue ZHAO , Tao Yang , Yuancheng Yang , Lei Liu , Di Wang , Kun Zhang , Wenxi Zhou , Zhiliang Xia , Zongliang Huo
IPC分类号： H01L27/108
CPC分类号： H01L27/10802
摘要： A three-dimensional (3D) memory device includes a memory cell, a top contact coupled to the memory cell, and a bottom contact coupled to the memory cell. The memory cell can include a pillar, an insulating layer surrounding the pillar, a first gate contact coupled to a word line, a second gate contact coupled to a plate line, and a third gate contact configured to control electrical charge conduction between the first gate contact and the second gate contact. The 3D memory device can utilize dynamic flash memory (DFM), increase storage efficiency, provide tri-gate control, provide different programming options, increase read, program, and erase operation rates, decrease leakage current, increase retention time, and decrease refresh rates.
-
公开(公告)号：US11716853B2
公开(公告)日：2023-08-01
申请号：US16895410
申请日：2020-06-08
发明人： Linchun Wu , Kun Zhang , Wenxi Zhou , Zhiliang Xia
摘要： Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes depositing a cover layer over a substrate, depositing a sacrificial layer over the cover layer, depositing a layer stack over the sacrificial layer, forming a channel layer extending through the layer stack and the sacrificial layer, performing a first epitaxial growth to deposit a first epitaxial layer on a side portion of the channel layer that is close to the substrate, removing the cover layer, and performing a second epitaxial growth to simultaneously thicken the first epitaxial layer and deposit a second epitaxial layer on the substrate. The layer stack includes first stack layers and second stack layers that are alternately stacked.
-
公开(公告)号：US11574922B2
公开(公告)日：2023-02-07
申请号：US16913611
申请日：2020-06-26
发明人： Kun Zhang , Wenxi Zhou , Zhiliang Xia , Zongliang Huo
IPC分类号： H01L27/11582 , H01L27/11524 , H01L27/11539 , H01L27/11556 , H01L27/1157 , H01L27/11573
摘要： Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, an N-type doped semiconductor layer above the memory stack, a plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer, and a source contact above the memory stack and in contact with the N-type doped semiconductor layer. An upper end of each of the plurality of channel structures is flush with or below a top surface of the N-type doped semiconductor layer.
-
公开(公告)号：US11552091B2
公开(公告)日：2023-01-10
申请号：US17313740
申请日：2021-05-06
发明人： Zhongwang Sun , Guangji Li , Kun Zhang , Ming Hu , Jiwei Cheng , Shijin Luo , Kun Bao , Zhiliang Xia
IPC分类号： H01L27/11556 , H01L27/11582 , H01L27/11573 , H01L27/11524 , H01L27/1157 , H01L27/11529
摘要： Embodiments of contact structures of a three-dimensional memory device and fabrication method thereof are disclosed. The three-dimensional memory structure includes a film stack disposed on a substrate, wherein the film stack includes a plurality of conductive and dielectric layer pairs, each conductive and dielectric layer pair having a conductive layer and a first dielectric layer. The three-dimensional memory structure also includes a staircase structure formed in the film stack, wherein the staircase structure includes a plurality of steps, each staircase step having two or more conductive and dielectric layer pairs. The three-dimensional memory structure further includes a plurality of coaxial contact structures formed in a first insulating layer over the staircase structure, wherein each coaxial contact structure includes one or more conductive and insulating ring pairs and a conductive core, each conductive and insulating ring pair having a conductive ring and an insulating ring.
-
公开(公告)号：US20230005941A1
公开(公告)日：2023-01-05
申请号：US17483204
申请日：2021-09-23
发明人： Kun Zhang , Wenxi Zhou , Wei Liu , Zhiliang Xia , Liang Chen , Yanhong Wang
IPC分类号： H01L27/11526 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11565 , H01L27/11573 , H01L27/11582
摘要： Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a first semiconductor assembly, a second semiconductor assembly, and an inter-assembly bonding layer between the first semiconductor assembly and the second semiconductor assembly. The first semiconductor assembly includes a first array structure and a first periphery structure. The first array structure includes a first memory stack having a plurality of interleaved stack conductive layers and stack dielectric layers. The first periphery structure includes a plurality of first peripheral circuits electrically connected to the first memory stack. The second semiconductor assembly includes a second array structure and a second periphery structure. The second array structure includes a second memory stack having a plurality of interleaved stack conductive layers and stack dielectric layers. The second periphery structure includes a plurality of second peripheral circuits electrically connected to the second memory stack.
-
公开(公告)号：US20230005860A1
公开(公告)日：2023-01-05
申请号：US17481040
申请日：2021-09-21
发明人： Liang Chen , Wei Liu , Yanhong Wang , Zhiliang Xia , Wenxi Zhou , Kun Zhang , Yuancheng Yang
IPC分类号： H01L23/00 , H01L25/065 , H01L25/18 , H01L25/00
摘要： In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells. The second semiconductor structure includes a first peripheral circuit of the array of memory cells. The first peripheral circuit includes a first transistor. The first semiconductor structure or the second semiconductor structure further includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor. The first peripheral circuit and the second peripheral circuit are stacked over one another.
-
公开(公告)号：US20230005857A1
公开(公告)日：2023-01-05
申请号：US17480897
申请日：2021-09-21
发明人： Liang Chen , Wei Liu , Yanhong Wang , Zhiliang Xia , Wenxi Zhou , Kun Zhang , Yuancheng Yang , Shiqi Huang
IPC分类号： H01L23/00 , H01L25/065 , H01L25/18 , H01L25/00
摘要： In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of NAND memory strings and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of NAND memory strings including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a third semiconductor layer in contact with the second transistor. The first peripheral circuit is between the first bonding interface and the second semiconductor layer. The third semiconductor layer is between the second peripheral circuit and the second bonding interface.
-
公开(公告)号：US20220392864A1
公开(公告)日：2022-12-08
申请号：US17354969
申请日：2021-06-22
发明人： Kun Zhang
IPC分类号： H01L23/00 , H01L25/065 , H01L25/18 , H01L23/48 , H01L25/00
摘要： Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a first semiconductor structure, a second semiconductor structure opposite to the first semiconductor structure, and an interface layer between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a memory stack having a plurality of interleaved stack conductive layers and stack dielectric layers. The second semiconductor structure includes a plurality of peripheral circuits electrically connected to the memory stack. The interface layer includes single crystalline silicon and a plurality of interconnects between the memory stack and the peripheral circuits.
-
-
-
-
-
-
-
-
-
搜索结果
139 条记录 (耗时 0.034 秒)
