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公开(公告)号：US12114498B2
公开(公告)日：2024-10-08
申请号：US16920218
申请日：2020-07-02
发明人： Linchun Wu , Kun Zhang , Wenxi Zhou , Zhiliang Xia
IPC分类号： H01L23/48 , H01L21/48 , H10B43/27 , H01L21/306
CPC分类号： H10B43/27 , H01L21/30604 , H01L21/30625
摘要： Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a stop layer, a polysilicon layer, a memory stack including interleaved stack conductive layers and stack dielectric layers, and a plurality of channel structures each extending vertically through the memory stack and the polysilicon layer, stopping at the stop layer.
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公开(公告)号：US12089413B2
公开(公告)日：2024-09-10
申请号：US17510752
申请日：2021-10-26
发明人： Yanwei Shi , Yanhong Wang , Cheng Gan , Liang Chen , Wei Liu , Zhiliang Xia , Wenxi Zhou , Kun Zhang , Yuancheng Yang
IPC分类号： H10B43/40 , G11C16/04 , G11C16/24 , H01L23/00 , H01L25/00 , H01L25/065 , H01L25/18 , H10B41/41
CPC分类号： H10B43/40 , G11C16/0483 , G11C16/24 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H10B41/41 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/14511
摘要： In certain aspects, a memory device includes an array of memory cells and a plurality of peripheral circuits coupled to the array of memory cells. The peripheral circuits include a first peripheral circuit including a recess gate transistor. The peripheral circuits also include a second peripheral circuit including a flat gate transistor.
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公开(公告)号：US12082411B2
公开(公告)日：2024-09-03
申请号：US17020383
申请日：2020-09-14
发明人： Kun Zhang , Zhong Zhang , Lei Liu , Wenxi Zhou , Zhiliang Xia
IPC分类号： H10B43/27 , H01L23/528 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/35 , H10B43/40
CPC分类号： H10B43/27 , H01L23/5283 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/35 , H10B43/40
摘要： Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, a plurality of channel structures each extending vertically through the memory stack, a semiconductor layer above and in contact with the plurality of channel structures, a plurality of source contacts above the memory stack and in contact with the semiconductor layer, a plurality of contacts through the semiconductor layer, and a backside interconnect layer above the semiconductor layer including a source line mesh in a plan view. The plurality of source contacts are distributed below and in contact with the source line mesh. A first set of the plurality of contacts are distributed below and in contact with the source line mesh.
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公开(公告)号：US12069854B2
公开(公告)日：2024-08-20
申请号：US17480998
申请日：2021-09-21
发明人： Kun Zhang , Yuancheng Yang , Wenxi Zhou , Wei Liu , Zhiliang Xia , Liang Chen , Yanhong Wang
IPC分类号： H10B41/20 , H01L25/065 , H10B41/41 , H10B43/20 , H10B43/40
CPC分类号： H10B41/20 , H01L25/0652 , H10B41/41 , H10B43/20 , H10B43/40
摘要： In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a first semiconductor layer, an array of NAND memory strings, and a first peripheral circuit of the array of NAND memory strings. Sources of the array of NAND memory strings are in contact with a first side of the first semiconductor layer. The first peripheral circuit includes a first transistor in contact with a second side of the first semiconductor layer opposite to the first side. The second semiconductor structure includes a second semiconductor layer and a second peripheral circuit of the array of NAND memory strings. The second peripheral circuit includes a second transistor in contact with the second semiconductor layer.
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公开(公告)号：US12058858B2
公开(公告)日：2024-08-06
申请号：US17117690
申请日：2020-12-10
发明人： Kun Zhang , Linchun Wu , Wenxi Zhou , Zhiliang Xia , Zongliang Huo
IPC分类号： H10B43/27 , H01L21/02 , H01L21/225 , H01L21/311 , H01L21/3115 , H01L21/3205 , H01L21/3213 , H01L21/3215 , H01L23/00 , H01L25/065 , H01L25/18 , H01L29/04 , H01L29/10 , H01L29/16 , H10B41/27
CPC分类号： H10B43/27 , H01L21/02164 , H01L21/2255 , H01L21/2257 , H01L21/31111 , H01L21/3115 , H01L21/32055 , H01L21/32133 , H01L21/32155 , H01L24/08 , H01L25/0657 , H01L25/18 , H01L29/04 , H01L29/1037 , H01L29/16 , H10B41/27 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
摘要： A 3D memory device includes a memory stack including interleaved stack conductive layers and stack dielectric layers, a semiconductor layer, and a channel structure extending vertically through the memory stack into the semiconductor layer. A first lateral dimension of a first portion of the channel structure facing the semiconductor layer is greater than a second lateral dimension of a second portion of the channel structure facing the memory stack. The channel structure includes a memory film and a semiconductor channel A first doping concentration of part of the semiconductor channel in the first portion of the channel structure is greater than a second doping concentration of part of the semiconductor channel in the second portion of the channel structure.
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公开(公告)号：US20240206181A1
公开(公告)日：2024-06-20
申请号：US18090915
申请日：2022-12-29
发明人： Di Wang , Yuancheng Yang , Lei Liu , Tao Yang , Kun Zhang , Dongxue Zhao , Wenxi Zhou , Zhiliang Xia , Zongliang Huo
IPC分类号： H10B43/40 , H01L23/528 , H10B41/27 , H10B41/40 , H10B43/27
CPC分类号： H10B43/40 , H01L23/5283 , H10B41/27 , H10B41/40 , H10B43/27
摘要： A memory device includes a semiconductor layer; a peripheral circuit disposed on the semiconductor layer; and an array of memory cells disposed aside the peripheral circuit on the semiconductor layer. Each of the memory cells includes a semiconductor body extending in a first direction, a first end of the semiconductor body is in contact with the semiconductor layer; a word line gate extending in a second direction perpendicular to the first direction; a plate line gate extending in the second direction; and a dielectric layer disposed between the semiconductor body and the word line gate and the plate line gate.
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公开(公告)号：US20240170424A1
公开(公告)日：2024-05-23
申请号：US18078898
申请日：2022-12-09
发明人： Kun Zhang , Wenxi Zhou , Jing Gao , Zhiliang Xia , Zongliang Huo
IPC分类号： H01L23/00 , H01L25/00 , H01L25/065 , H01L25/18
CPC分类号： H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/14511
摘要： Three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. In certain aspects, a method for forming a 3D memory device can comprise forming a first semiconductor structure, comprising forming a stack structure on a first substrate, and forming a gate line slit structure including a filling structure penetrating the stack structure and extending into the first substrate. The method can further comprise forming a second semiconductor structure including a periphery circuit on a second substrate, and bonding the second semiconductor structure to the first semiconductor structure. The method can further comprise removing a portion of the first substrate and a portion of the gate line slit structure extended into the first substrate, and forming a supplemental semiconductor layer on a remaining portion of the first substrate.
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公开(公告)号：US11948901B2
公开(公告)日：2024-04-02
申请号：US17113605
申请日：2020-12-07
发明人： Kun Zhang
CPC分类号： H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H10B41/27 , H10B43/27 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/14511
摘要： Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a stack of layers. The stack of layers includes a common source layer, gate layers and insulating layers disposed on a substrate. The gate layers and insulating layers are stacked alternatingly. Then, the semiconductor device includes an array of channel structures formed in an array region. The channel structure extends through the stack of layers and forms a stack of transistors in a series configuration. The channel structure includes a channel layer that is in contact with the common source layer. The common source layer extends over the array region and a staircase region. The semiconductor device includes a contact structure disposed in the staircase region. The contact structure forms a conductive connection with the common source layer.
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公开(公告)号：US20240074181A1
公开(公告)日：2024-02-29
申请号：US17896959
申请日：2022-08-26
发明人： Linchun Wu , Kun Zhang , Wenxi Zhou , Cuicui Kong , Shuangshuang Wu , Zhiliang Xia , Zongliang Huo
IPC分类号： H01L27/11582 , H01L23/528 , H01L27/11519 , H01L27/11556 , H01L27/11565
CPC分类号： H01L27/11582 , H01L23/5283 , H01L27/11519 , H01L27/11556 , H01L27/11565
摘要： A memory device includes a stack structure, channel structures, and a slit structure. The stack structure includes interleaved conductive layers and dielectric layers, and the conductive layers include a plurality of word lines. Each of the channel structures extends vertically through the stack structure. The slit structure extends vertically through the stack structure. An outer region of the stack structure includes a staircase structure, and the interleaved conductive layers and dielectric layers in a bottom portion of the stack structure are wider than the interleaved conductive layers and dielectric layers in a top portion of the stack structure. A first outer width of the slit structure in the bottom portion of the stack structure is greater than a second outer width of the slit structure in the top portion of the stack structure.
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公开(公告)号：US20240063140A1
公开(公告)日：2024-02-22
申请号：US17891064
申请日：2022-08-18
发明人： Jingtao Xie , Bingjie Yan , Kun Zhang , Wenxi Zhou , Zhiliang Xia , Zongliang Huo
IPC分类号： H01L23/00 , H01L23/535 , H01L27/11556 , H01L27/11582
CPC分类号： H01L23/562 , H01L23/535 , H01L27/11556 , H01L27/11582
摘要： A three-dimensional (3D) memory device includes a stack, a plurality of contact structures, and a plurality of support structures. The stack in an insulating structure includes conductive layers and dielectric layers stacked alternatingly, and the stack includes a staircase structure. Each contact structure extends through the insulating structure and is in contact with a respective conductive layer in the staircase structure. The support structures extend through the stack in the staircase structure. The contact structures are arranged in a first row and a second row, the first row of contact structures is in electrical contact with the peripheral device, and the second row of contact structures is in electrical insulation with the peripheral device.
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