公开(公告)号：US06664141B1

公开(公告)日：2003-12-16

申请号：US09991187

申请日：2001-11-14

申请人： Ruggero Castagnetti ,  Prabhakar Pati Tripathi ,  Ramnath Venkatraman

发明人： Ruggero Castagnetti ,  Prabhakar Pati Tripathi ,  Ramnath Venkatraman

IPC分类号： H01L2182

CPC分类号： H01L21/84 ,  H01L23/5258 ,  H01L27/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method of forming a semiconductor device fuse and a semiconductor device fuse structure. A first dielectric layer is formed on top of a metal layer in a semiconductor device. The dielectric layer is patterned to provide access to at least two contacts in the metal layer. A conductive metal layer is deposited and patterned to form a fuse between the fuse contacts. A second dielectric layer is deposited on the conductive metal layer.

摘要翻译： 本发明提供一种形成半导体器件熔丝和半导体器件熔丝结构的方法。 在半导体器件中的金属层的顶部上形成第一电介质层。 图案化介电层以提供对金属层中的至少两个触点的访问。 导电金属层被沉积​​并图案化以在熔丝触点之间形成熔丝。 第二介电层沉积在导电金属层上。

公开(公告)号：US06687114B1

公开(公告)日：2004-02-03

申请号：US10403433

申请日：2003-03-31

申请人： Arvind Kamath ,  Ruggero Castagnetti

发明人： Arvind Kamath ,  Ruggero Castagnetti

IPC分类号： H01G4228

CPC分类号： H01L27/1087 ,  H01L27/10894 ,  H01L29/66181

摘要： A memory cell having a transistor and a capacitor formed in a silicon substrate. The capacitor is formed with a lower electrically conductive plate etched in a projected surface area of the silicon substrate. The lower electrically conductive plate has at least one cross section in the shape of a vee, where the sides of the vee are disposed at an angle of about fifty-five degrees from a top surface of the silicon substrate. The surface area of the lower electrically conductive plate is about seventy-three percent larger than the projected surface area of the silicon substrate in which the lower electrically conductive plate is etched. A capacitor dielectric layer is formed of a first deposited dielectric layer, which is disposed adjacent the lower electrically conductive plate. A top electrically conductive plate is disposed adjacent the capacitor dielectric layer and opposite the lower electrically conductive plate. A transistor is formed having source and drain regions separated by a channel region, and a gate dielectric layer formed of the first deposited dielectric layer.

摘要翻译： 具有在硅衬底中形成的晶体管和电容器的存储单元。 电容器形成有在硅衬底的投影表面区域中蚀刻的下导电板。 下导电板具有至少一个vee形状的横截面，其中，vee的侧面与硅衬底的顶表面成约五十五度的角度。 下导电板的表面积比其中蚀刻下导电板的硅衬底的投影表面积大约百分之七点三。 电容器介电层由邻近下导电板设置的第一沉积介电层形成。 顶部导电板设置在电容器电介质层附近并与下部导电板相对。 晶体管形成为具有由沟道区域分离的源极和漏极区域以及由第一沉积介电层形成的栅极电介质层。

公开(公告)号：US20050122120A1

公开(公告)日：2005-06-09

申请号：US10727719

申请日：2003-12-04

申请人： Franklin Duan ,  Subramanian Ramesh ,  Ruggero Castagnetti

发明人： Franklin Duan ,  Subramanian Ramesh ,  Ruggero Castagnetti

IPC分类号： G01R27/08 ,  G01R31/26 ,  G11C29/02

CPC分类号： G11C29/50008 ,  G11C11/41 ,  G11C29/02 ,  G11C29/022

摘要： Test structures are provided for accurately quantifying shared contact resistance. The test structures are built based upon an actual memory cell, which is self-aligning to allow shared contact chains through an array of test cells. A main array of test cells is built to provide a chain of shared contact resistance. Using the main array of test cells, a resistance in the shared contact chain may be measured. Supplemental arrays of test cells is built to provide a chain of poly side resistance, a chain of island side resistance, a chain of island connection line resistance, and a chain of poly connection resistance. A tester measures resistance using the test structures and uses the values to accurately determine shared contact resistance.

摘要翻译： 提供了测试结构，用于准确地量化共享接触电阻。 测试结构基于实际的存储单元构建，该存储单元是自对准的，以允许通过测试单元阵列的共享接触链。 测试电池的主要阵列被构建以提供共享接触电阻链。 使用测试电池的主阵列，可以测量共享接触链中的电阻。 测试电池的补充阵列被构建以提供聚侧电阻链，岛侧电阻链，岛连接线电阻链和多连接电阻链。 测试者使用测试结构测量电阻，并使用这些值来准确地确定共同的接触电阻。

公开(公告)号：US06978407B2

公开(公告)日：2005-12-20

申请号：US10445437

申请日：2003-05-27

申请人： Franklin L. Duan ,  Subramanian Ramesh ,  Ruggero Castagnetti

发明人： Franklin L. Duan ,  Subramanian Ramesh ,  Ruggero Castagnetti

IPC分类号： G11C29/00 ,  H01L23/544 ,  H01L27/02 ,  H01L27/105

CPC分类号： H01L22/34 ,  G11C29/006 ,  G11C2029/0403 ,  H01L27/0207 ,  H01L27/105

摘要： A self-aligning memory cell design is provided to allow testing of transistors in every cell of a memory circuit. A test array of these cells is fabricated with contact pads in each cell for specific components in the cell. Then, metal lines are provided to couple the contact pads in the test array. The whole test array is then probed via these metal lines. Tests may then be performed to detect random and systematic transistor degradation electrically for all cells in the circuit. Different components in the memory design may be tested by providing contact pads for the components of interest and providing metal lines coupling the contact pads.

摘要翻译： 提供自对准存储单元设计以允许对存储器电路的每个单元中的晶体管进行测试。 这些电池的测试阵列在每个电池中用接触垫制造，用于电池中的特定组分。 然后，提供金属线以耦合测试阵列中的接触焊盘。 然后通过这些金属线探测整个测试阵列。 然后可以执行测试以检测电路中的所有单元电子的随机和系统的晶体管劣化。 存储器设计中的不同部件可以通过为感兴趣的部件提供接触焊盘并且提供耦合接触焊盘的金属线来测试。

公开(公告)号：US06977512B2

公开(公告)日：2005-12-20

申请号：US10727719

申请日：2003-12-04

申请人： Franklin Duan ,  Subramanian Ramesh ,  Ruggero Castagnetti

发明人： Franklin Duan ,  Subramanian Ramesh ,  Ruggero Castagnetti

IPC分类号： G01R27/08 ,  G01R31/26 ,  G11C29/02

CPC分类号： G11C29/50008 ,  G11C11/41 ,  G11C29/02 ,  G11C29/022

摘要： Test structures are provided for accurately quantifying shared contact resistance. The test structures are built based upon an actual memory cell, which is self-aligning to allow shared contact chains through an array of test cells. A main array of test cells is built to provide a chain of shared contact resistance. Using the main array of test cells, a resistance in the shared contact chain may be measured. Supplemental arrays of test cells is built to provide a chain of poly side resistance, a chain of island side resistance, a chain of island connection line resistance, and a chain of poly connection resistance. A tester measures resistance using the test structures and uses the values to accurately determine shared contact resistance.

公开(公告)号：US6144076A

公开(公告)日：2000-11-07

申请号：US207395

申请日：1998-12-08

申请人： Helmut Puchner ,  Shih-Fen Huang ,  Ruggero Castagnetti

发明人： Helmut Puchner ,  Shih-Fen Huang ,  Ruggero Castagnetti

IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/76

CPC分类号： H01L21/823892 ,  H01L21/76237 ,  H01L27/0921

摘要： A multiple well formation is provided in a CMOS region of a semiconductor substrate to provide enhanced latchup protection for one or more CMOS transistors formed in the wells. The structure comprises an N well extending from the substrate surface down into the substrate, a buried P well formed in the substrate beneath the N well, a second P well extending from the substrate surface down into the substrate, and an isolation region formed in the substrate between the N well and the second P well. The buried P well may extend beneath both the N well and the second P well in the substrate. In a preferred embodiment of the invention, the N well and the second P well are each implanted in the substrate at an energy level sufficient to provide a dopant concentration peak in the substrate below the depth of the isolation region to provide punch through protection and to provide a channel stop beneath the isolation region by proving a P-N junction between the N well and P well beneath the isolation region. The dopant concentration level peak of the dopants forming the buried P well in the substrate will be located below the dopant concentration level peak of the N well a minimum distance sufficient to inhibit reduction of the effective depth of the N well, and a maximum distance not exceeding the maximum distance which will still provide enhanced latchup protection to one or more transistors formed in the CMOS region.

摘要翻译： 在半导体衬底的CMOS区域中提供多阱形成，以为形成在阱中的一个或多个CMOS晶体管提供增强的闭锁保护。 该结构包括从衬底表面向下延伸到衬底中的N阱，在N阱下方的衬底中形成的掩埋P阱，从衬底表面向下延伸到衬底中的第二P阱以及形成在衬底中的隔离区 N阱和第二P阱之间的衬底。 掩埋的P阱可以在衬底中的N阱和第二P阱的下方延伸。 在本发明的一个优选实施方案中，N阱和第二P阱各自以足以在衬底中的掺杂剂浓度峰值（在低于隔离区域的深度）提供掺杂剂浓度峰值的能级注入到衬底中，以提供穿通保护，并且 通过在隔离区之下的N阱和P阱之间提供PN结，在隔离区之下提供通道停止。 在衬底中形成掩埋P阱的掺杂剂的掺杂剂浓度水平峰值将位于N阱的掺杂剂浓度水平峰值以下，其最小距离足以抑制N阱的有效深度的减小，并且最大距离不 超过仍将为在CMOS区域中形成的一个或多个晶体管提供增强的闭锁保护的最大距离。

公开(公告)号：US06778462B1

公开(公告)日：2004-08-17

申请号：US10431940

申请日：2003-05-08

申请人： Ruggero Castagnetti ,  Ramnath Ventatraman ,  Subramanian Ramesh

发明人： Ruggero Castagnetti ,  Ramnath Ventatraman ,  Subramanian Ramesh

IPC分类号： G11C800

CPC分类号： G11C8/14 ,  G11C8/16

摘要： The present invention provides a method and apparatus for providing dual-port capability to an SRAM array. The internal nodes of two single-port memory cells are connected to each other through metal-layer programming to form a dual-port memory cell. In a preferred embodiment, a split word line design is used for each single-port memory cell, to facilitate dual-port memory access while minimizing the need for IC layout space. An additional benefit of the present invention is that it allows “slices” of a memory array to be converted into dual-port memory, so as to allow both single-port and dual-port memory cells in the same memory array.

摘要翻译： 本发明提供了一种向SRAM阵列提供双端口能力的方法和装置。 两个单端口存储单元的内部节点通过金属层编程相互连接形成双端口存储单元。 在优选实施例中，分割字线设计用于每个单端口存储器单元，以便于双端口存储器访问，同时最小化对IC布局空间的需要。 本发明的另外的好处在于它允许将存储器阵列的“切片”转换成双端口存储器，从而允许同一存储器阵列中的单端口和双端口存储器单元。

公开(公告)号：US06586291B1

公开(公告)日：2003-07-01

申请号：US10214618

申请日：2002-08-08

申请人： Arvind Kamath ,  Ruggero Castagnetti

发明人： Arvind Kamath ,  Ruggero Castagnetti

IPC分类号： H01L218238

CPC分类号： H01L27/1087 ,  H01L27/10894 ,  H01L29/66181

摘要： A memory cell having a transistor and a capacitor formed in a silicon substrate. The capacitor is formed with a lower electrically conductive plate etched in a projected surface area of the silicon substrate. The lower electrically conductive plate has at least one cross section in the shape of a vee, where the sides of the vee are disposed at an angle of about fifty-five degrees from a top surface of the silicon substrate. The surface area of the lower electrically conductive plate is about seventy-three percent larger than the projected surface area of the silicon substrate in which the lower electrically conductive plate is etched. A capacitor dielectric layer is formed of a first deposited dielectric layer, which is disposed adjacent the lower electrically conductive plate. A top electrically conductive plate is disposed adjacent the capacitor dielectric layer and opposite the lower electrically conductive plate. A transistor is formed having source and drain regions separated by a channel region, and a gate dielectric layer formed of the first deposited dielectric layer.

摘要翻译： 具有在硅衬底中形成的晶体管和电容器的存储单元。 电容器形成有在硅衬底的投影表面区域中蚀刻的下导电板。 下导电板具有至少一个vee形状的横截面，其中，vee的侧面与硅衬底的顶表面成约五十五度的角度。 下导电板的表面积比其中蚀刻下导电板的硅衬底的投影表面积大约百分之七十三。 电容器介电层由邻近下导电板设置的第一沉积介电层形成。 顶部导电板设置在电容器电介质层附近并与下部导电板相对。 晶体管形成为具有由沟道区域分离的源极和漏极区域以及由第一沉积介电层形成的栅极电介质层。