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159 条记录 (耗时 0.044 秒)

    Magnetoresistive element and method of manufacturing the same
    42.
    发明授权
    Magnetoresistive element and method of manufacturing the same 有权
    磁阻元件及其制造方法

    公开(公告)号：US08081505B2

    公开(公告)日：2011-12-20

    申请号：US12556389

    申请日：2009-09-09

    申请人： Takeshi Kajiyama ,  Yoshiaki Asao ,  Shigeki Takahashi ,  Minoru Amano ,  Kuniaki Sugiura

    发明人： Takeshi Kajiyama ,  Yoshiaki Asao ,  Shigeki Takahashi ,  Minoru Amano ,  Kuniaki Sugiura

    IPC分类号： H01L29/82

    CPC分类号： H01L27/228 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

    摘要： A magnetoresistive element includes a stacked structure including a fixed layer having a fixed direction of magnetization, a recording layer having a variable direction of magnetization, and a nonmagnetic layer sandwiched between the fixed layer and the recording layer, a first protective film covering a circumferential surface of the stacked structure, and made of silicon nitride, and a second protective film covering a circumferential surface of the first protective film, and made of silicon nitride. A hydrogen content in the first protective film is not more than 4 at %, and a hydrogen content in the second protective film is not less than 6 at %.

    摘要翻译： 磁阻元件包括堆叠结构，其包括具有固定磁化方向的固定层，具有可变磁化方向的记录层和夹在固定层和记录层之间的非磁性层，覆盖周向表面的第一保护膜 层叠结构，由氮化硅制成，第二保护膜覆盖第一保护膜的周面，由氮化硅构成。 第一保护膜中的氢含量不大于4原子％，第二保护膜中的氢含量不低于6原子％。

    Semiconductor device having separation region
    45.
    发明授权
    Semiconductor device having separation region 失效
    具有分离区域的半导体器件

    公开(公告)号：US07388255B2

    公开(公告)日：2008-06-17

    申请号：US11598650

    申请日：2006-11-14

    申请人： Takashi Nakano ,  Shigeki Takahashi

    发明人： Takashi Nakano ,  Shigeki Takahashi

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7824 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/7825

    摘要： A semiconductor device includes: a semiconductor substrate; a separation region in the substrate; an embedded layer; a channel forming region; a source region; a drain region; a first electrode for the source region; a second electrode for the channel forming region; a third electrode for the drain region; a trench penetrating the channel forming region between the source region and the drain region; a trench gate electrode in the trench; an offset layer on a portion to be a current path provided by the trench gate electrode; and an electric field relaxation layer under the channel forming region and the offset layer connected to the channel forming region and covering a bottom of the trench.

    摘要翻译： 半导体器件包括：半导体衬底; 衬底中的分离区域; 嵌入层; 通道形成区域; 源区; 漏区; 用于源区的第一电极; 用于沟道形成区域的第二电极; 用于漏区的第三电极; 穿过源极区域和漏极区域之间的沟道形成区域的沟槽; 沟槽中的沟槽栅电极; 由沟槽栅电极提供的作为电流路径的部分上的偏移层; 以及在沟道形成区域下方的电场弛豫层，并且偏移层连接到沟道形成区域并覆盖沟槽的底部。

    Connector in which two housings holding a cable are firmly engaged with each other
    47.
    发明申请
    Connector in which two housings holding a cable are firmly engaged with each other 有权
    连接器，其中保持电缆的两个壳体彼此牢固地接合

    公开(公告)号：US20070167066A1

    公开(公告)日：2007-07-19

    申请号：US11645467

    申请日：2006-12-26

    申请人： Seiichi Hara ,  Kiminobu Tabata ,  Takeshi Kai ,  Tsutomu Fukui ,  Masaru Shinmura ,  Tadashi Inazu ,  Shigeki Takahashi

    发明人： Seiichi Hara ,  Kiminobu Tabata ,  Takeshi Kai ,  Tsutomu Fukui ,  Masaru Shinmura ,  Tadashi Inazu ,  Shigeki Takahashi

    IPC分类号： H01R13/58

    CPC分类号： H01R13/582

    摘要： A connector includes two housings coupled with each other to hold a cable therebetween. One of the housings includes a cable receiving portion for receiving the cable, a restricting portion adjacent to the cable receiving portion, a first wall portion formed outside the restricting portion and defining a space between the first wall portion and the restricting portion, and a first engaging portion inwardly protruding from the first wall portion. Another of the housings includes a cable pressing portion for pressing the cable towards the cable receiving portion and the restricting portion, and a second wall portion formed adjacent to the cable pressing portion and inserted into the space. The second wall portion has a second engaging portion extending outward from the second wall portion. The first and the second engaging potions are engaged with each other to prevent the housings from separating from each other.

    摘要翻译： 连接器包括彼此联接以在其间保持电缆的两个壳体。 其中一个壳体包括用于接收电缆的电缆接收部分，与电缆接收部分相邻的限制部分，形成在限制部分外部并限定第一壁部分和限制部分之间的空间的第一壁部分，以及第一 接合部从第一壁部向内突出。 另一个壳体包括用于将电缆朝向电缆接收部分和限制部分按压的电缆按压部分，以及邻近电缆按压部分形成并插入到该空间中的第二壁部分。 第二壁部具有从第二壁部向外延伸的第二接合部。 第一和第二接合部分彼此接合以防止壳体彼此分离。

    Semiconductor output circuit
    48.
    发明授权
    Semiconductor output circuit 有权
    半导体输出电路

    公开(公告)号：US07183802B2

    公开(公告)日：2007-02-27

    申请号：US11079517

    申请日：2005-03-15

    申请人： Yoshinori Arashima ,  Hirofumi Abe ,  Shigeki Takahashi

    发明人： Yoshinori Arashima ,  Hirofumi Abe ,  Shigeki Takahashi

    IPC分类号： H03K19/0175

    CPC分类号： H03K17/0822 ,  H01L27/0266 ,  H01L29/0696 ,  H01L29/7816

    摘要： The semiconductor output circuit of the invention has an insulated gate transistor including a first terminal, a second terminal and a gate terminal, a conductive state of the insulated gate transistor being controlled by a drive circuit connected to the gate terminal, a capacitive element and a first resistor connected in series between the second terminal and the gate terminal, and a second resistor connected between the gate terminal and the first terminal. The insulated gate transistor has a cell area formed on a semiconductor substrate, in which a plurality of unit cells each defining a unit transistor connected between the first and second terminals are laid out. The second resistor has such a resistance that all of the unit transistors defined by the unit cells are turned on uniformly when electrostatic discharge is applied to the first or second terminal.

    摘要翻译： 本发明的半导体输出电路具有包括第一端子，第二端子和栅极端子的绝缘栅极晶体管，绝缘栅极晶体管的导通状态由连接到栅极端子的驱动电路，电容元件和 第一电阻器串联连接在第二端子和栅极端子之间，第二电阻器连接在栅极端子和第一端子之间。 绝缘栅极晶体管具有形成在半导体衬底上的单元区域，其中布置了连接在第一和第二端子之间的单元晶体管的多个单位单元。 第二电阻器具有这样的电阻，即当静电放电施加到第一或第二端子时，由单电池限定的所有单位晶体管均匀地导通。

    Controller of graphic equalizer
    49.
    发明申请
    Controller of graphic equalizer 有权
    图形均衡器控制器

    公开(公告)号：US20060204021A1

    公开(公告)日：2006-09-14

    申请号：US11367087

    申请日：2006-03-02

    申请人： Masaaki Okabayashi ,  Shigeki Takahashi

    发明人： Masaaki Okabayashi ,  Shigeki Takahashi

    IPC分类号： H03G5/00 ,  H04B3/14 ,  H01P9/00

    CPC分类号： H03G5/025

    摘要： An apparatus is provided for controlling a graphic equalizer which is implemented by digital filters, each being assignable to a frequency band for regulating a level of the frequency band. In the apparatus, a set of control devices are provided in correspondence to respective frequency bands, each control device being operable to specify the level of the corresponding frequency band to either of a reference level or other level than the reference level. An assignment section operates when a number of the digital filters is less than a total number of the frequency bands, for assigning the digital filters to the frequency bands which are specified with the levels other than the reference level. A control section controls remaining digital filters which are not assigned to any of the frequency bands in a through state. A disabling section operates when the assignment section assigns all of the digital filters to the frequency bands which are specified with levels other than the reference level, for disabling operation of a control device which currently specifies the reference level.

    摘要翻译： 提供一种用于控制由数字滤波器实现的图形均衡器的装置，每个滤波器可分配给用于调节频带电平的频带。 在该装置中，与各频带相对应地提供一组控制装置，每个控制装置可操作以将相应频带的电平指定为参考电平或与基准电平相比的其它电平。 当多个数字滤波器小于频带的总数时，分配部分操作，用于将数字滤波器分配给用除参考电平之外的电平指定的频带。 控制部分控制没有分配给通过状态的任何频带的剩余数字滤波器。 禁用部分在分配部分将所有数字滤波器分配给以与参考电平以外的电平指定的频带时进行操作，以禁止当前指定参考电平的控制装置的操作。