公开(公告)号：US20250022915A1

公开(公告)日：2025-01-16

申请号：US18899522

申请日：2024-09-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ali RAZAVIEH ,  Haiting WANG

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a device with a vertical nanowire channel region and methods of manufacture. The structure includes: a bottom source/drain region; a top source/drain region; a gate structure extending between the bottom source/drain region and the top source/drain region; and a vertical nanowire in a channel region of the gate structure.

公开(公告)号：US12193243B2

公开(公告)日：2025-01-07

申请号：US17650084

申请日：2022-02-07

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Desmond Jia Jun Loy ,  Eng Huat Toh ,  Shyue Seng Tan

IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20

Abstract: The disclosed subject matter relates generally to structures, memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices having two resistive layers and a conductive layer arranged between two electrodes. The present disclosure provides a memory device including a first electrode above an interlayer dielectric region, a second electrode above the interlayer dielectric region, the second electrode is laterally adjacent to the first electrode, a conductive layer between the first electrode and the second electrode, in which the conductive layer is electrically isolated, a first resistive layer between the first electrode and the conductive layer, and a second resistive layer between the second electrode and the conductive layer.

公开(公告)号：US12183814B1

公开(公告)日：2024-12-31

申请号：US18615615

申请日：2024-03-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Steven J. Bentley ,  Francois Hebert ,  Lawrence Selvaraj Susai ,  Johnatan A Kantarovsky ,  Michael Zierak ,  Mark D. Levy ,  John Ellis-Monaghan

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to multi-channel transistors and methods of manufacture. The structure includes: a gate structure; a single channel layer in a channel region under the gate structure; a drift region adjacent to the gate structure; and multiple channel layers in the drift region coupled to the single channel layer under the gate structure.

公开(公告)号：US20240429237A1

公开(公告)日：2024-12-26

申请号：US18340463

申请日：2023-06-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anton TOKRANOV ,  Man GU ,  Eric Scott KOZARSKY ,  George MULFINGER ,  Hong YU

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes an insulating layer, a first semiconductor layer over the insulating layer, a diffusion break structure between a first active region and a second active region and including a first insulating pattern over the insulating layer and an opening over the first insulating pattern, and a conductive gate material over the opening.

公开(公告)号：US12176405B1

公开(公告)日：2024-12-24

申请号：US18664386

申请日：2024-05-15

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Khee Yong Lim ,  Xinfu Liu ,  Xiao Mei Elaine Low

IPC: H01L29/417 ,  H01L21/764 ,  H01L29/423 ,  H01L29/66

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor layer, a first raised source/drain region on the semiconductor layer, a second raised source/drain region on the semiconductor layer, a gate electrode laterally between the first raised source/drain region and the second raised source/drain region, a first airgap laterally between the first raised source/drain region and the gate electrode, and a second airgap laterally between the second raised source/drain region and the gate electrode. The gate electrode includes a first section and a second section between the first section and the semiconductor layer, the first section of the gate electrode has a first width, the second section of the gate electrode has a second width, and the first width is greater than the second width.

公开(公告)号：US12170329B2

公开(公告)日：2024-12-17

申请号：US17692218

申请日：2022-03-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anupam Dutta ,  Vvss Satyasuresh Choppalli ,  Rajendran Krishnasamy

IPC: H01L29/78 ,  H01L21/3215 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66

Abstract: According to various embodiments, there is provided a MOSFET device. The MOSFET device may include a substrate; a first doped region disposed in the substrate; a second doped region disposed in the substrate, wherein the first doped region and the second doped region are laterally adjacent to each other; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a gate disposed on the substrate, over the first and second doped regions, and between the third and fourth doped regions; and at least one high resistance region embedded in at least the second doped region, wherein the first doped region has a first conductivity type, wherein the second doped region, the third doped region, and the fourth doped region have a second conductivity type, wherein the first conductivity type and the second conductivity type are different.

公开(公告)号：US12170313B2

公开(公告)日：2024-12-17

申请号：US18324637

申请日：2023-05-26

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  Steven M. Shank ,  Rajendran Krishnasamy

IPC: H01L29/06 ,  H01L21/763 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.

公开(公告)号：US20240405019A1

公开(公告)日：2024-12-05

申请号：US18327107

申请日：2023-06-01

Applicant: GlobalFoundries U.S. Inc.

Inventor： Marvin G.L. Montaque ,  Cathryn J. Christiansen ,  Craig B. Beucler ,  Timothy W. Kemerer

IPC: H01L27/06 ,  H01L21/8249

Abstract: A structure includes a first gate structure spaced from a second gate structure in a field effect transistor (FET) area of a substrate. A polysilicon resistor is in a space between the first gate structure and the second gate structure. The polysilicon resistor has a lower surface that is farther from the substrate than lower surfaces of the polysilicon bodies of the first and second gate structures. The polysilicon resistor may have a different polarity dopant compared to at least one of the polysilicon bodies of the first and second gate structures.

公开(公告)号：US20240402426A1

公开(公告)日：2024-12-05

申请号：US18203321

申请日：2023-05-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Ryan Sporer ,  Karen Nummy

IPC: G02B6/124 ,  G02B6/13

Abstract: Structures for a photonics chip that include a reflector and methods of forming such structures. The structure comprises a reflector including a dielectric layer on a semiconductor substrate, a plurality of trenches in the dielectric layer, and a reflector layer. Each trench includes a plurality of sidewalls, and the reflector layer includes a portion on the sidewalls of each trench. The structure further comprises a photonic component over the reflector.

公开(公告)号：US12159926B2

公开(公告)日：2024-12-03

申请号：US18373598

申请日：2023-09-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Alexander Derrickson ,  Jagar Singh ,  Vibhor Jain ,  Andreas Knorr ,  Alexander Martin ,  Judson R. Holt ,  Zhenyu Hu

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.