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    Wrap around phase change memory
    2.
    发明授权
    Wrap around phase change memory 有权
    包围相变记忆

    公开(公告)号：US08963116B2

    公开(公告)日：2015-02-24

    申请号：US13664412

    申请日：2012-10-30

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Khee Yong Lim ,  Zufa Zhang

    IPC: H01L47/00 ,  H01L21/20 ,  G11C11/00

    CPC classification number: H01L45/16 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/128 ,  H01L45/141 ,  H01L45/144

    Abstract: A device is disclosed. The device includes a top electrode, a bottom electrode and a storage element between the top and bottom electrodes. The storage element includes a heat generating element disposed on the bottom electrode, a phase change element wrapping around an upper portion of the heat generating element, and a dielectric liner sandwiched between the phase change element and the heat generating element.

    Abstract translation: 公开了一种设备。 该装置包括顶部电极，底部电极和位于顶部和底部电极之间的存储元件。 存储元件包括设置在底部电极上的发热元件，围绕发热元件的上部缠绕的相变元件和夹在相变元件和发热元件之间的电介质衬垫。

    Integrated circuits having improved split-gate nonvolatile memory devices and methods for fabrication of same
    7.
    发明授权
    Integrated circuits having improved split-gate nonvolatile memory devices and methods for fabrication of same 有权
    具有改进的分离式非易失性存储器件的集成电路及其制造方法

    公开(公告)号：US08945997B2

    公开(公告)日：2015-02-03

    申请号：US13929393

    申请日：2013-06-27

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Zufa Zhang ,  Khee Yong Lim ,  Elgin Quek

    IPC: H01L21/82 ,  H01L29/792 ,  H01L29/66

    CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L29/42344 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/66833 ,  H01L29/792

    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit having a split-gate nonvolatile memory device includes forming a charge storage structure overlying a semiconductor substrate and having a first sidewall and a second sidewall and forming an interior cavity. The method forms a control gate in the interior cavity. Further, the method forms a first select gate overlying the semiconductor substrate and adjacent the first sidewall. A first memory cell is formed by the control gate and the first select gate. The method also forms a second select gate overlying the semiconductor substrate and adjacent the second sidewall. A second memory cell is formed by the control gate and the second select gate.

    Abstract translation: 提供了用于制造集成电路的集成电路和方法。 一种用于制造具有分离栅非易失性存储器件的集成电路的示例性方法包括形成覆盖半导体衬底并具有第一侧壁和第二侧壁并形成内腔的电荷存储结构。 该方法在内腔中形成控制门。 此外，该方法形成覆盖半导体衬底并且邻近第一侧壁的第一选择栅极。 第一存储单元由控制栅极和第一选择栅极形成。 该方法还形成覆盖半导体衬底并邻近第二侧壁的第二选择栅极。 第二存储单元由控制栅极和第二选择栅极形成。

    Field-effect transistors with airgap spacers
    8.
    发明授权
    Field-effect transistors with airgap spacers 有权

    公开(公告)号：US12176405B1

    公开(公告)日：2024-12-24

    申请号：US18664386

    申请日：2024-05-15

    Applicant: GlobalFoundries Singapore Pte. Ltd.

    Inventor： Khee Yong Lim ,  Xinfu Liu ,  Xiao Mei Elaine Low

    IPC: H01L29/417 ,  H01L21/764 ,  H01L29/423 ,  H01L29/66

    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor layer, a first raised source/drain region on the semiconductor layer, a second raised source/drain region on the semiconductor layer, a gate electrode laterally between the first raised source/drain region and the second raised source/drain region, a first airgap laterally between the first raised source/drain region and the gate electrode, and a second airgap laterally between the second raised source/drain region and the gate electrode. The gate electrode includes a first section and a second section between the first section and the semiconductor layer, the first section of the gate electrode has a first width, the second section of the gate electrode has a second width, and the first width is greater than the second width.

    Image sensor with reduced capacitance transfer gate
    10.
    发明授权
    Image sensor with reduced capacitance transfer gate 有权

    公开(公告)号：US11152410B2

    公开(公告)日：2021-10-19

    申请号：US16721837

    申请日：2019-12-19

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Khee Yong Lim ,  Chia Ching Yeo ,  Kiok Boone Elgin Quek

    IPC: H01L27/146 ,  H04N5/374 ,  H01L29/423

    Abstract: An image sensor pixel comprises a semiconductor substrate and a gate having a dielectric layer with a first section and a second section over the semiconductor substrate. The first section of the dielectric layer is thinner than the second section. A photodiode is disposed substantially beneath the gate. A gate well region is disposed beneath the gate and overlying the photodiode. A first doped semiconductor region separates the gate well region from a second doped semiconductor region. The second doped semiconductor region is in the semiconductor substrate and is adjacent to the gate.

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