公开(公告)号：US4479099A

公开(公告)日：1984-10-23

申请号：US374656

申请日：1982-05-04

申请人： Masaaki Atobe

发明人： Masaaki Atobe

IPC分类号： H03K7/06 ,  H04L27/20

CPC分类号： H03K7/06 ,  H04L27/20

摘要： A 2.sup.N -phase phase modulator is formed from a plurality of series-connected 2-phase phase modulators. Each of the 2-phase phase modulators includes an Exclusive OR gate receiving at one input terminal one of a plurality of digital data sets. The first phase modulator receives a carrier signal at its other input terminal, and all subsequent phase modulators receive an output from a previous phase modulator through a 1/2 frequency divider.

摘要翻译： 2N相位调制器由多个串联连接的2相相位调制器形成。 两相相位调制器中的每一个包括在一个输入端接收多个数字数据集中的一个的异或门。 第一相位调制器在其另一输入端接收载波信号，所有后续的相位调制器通过1/2分频器接收来自前一相位调制器的输出。

公开(公告)号：US4476480A

公开(公告)日：1984-10-09

申请号：US288450

申请日：1981-07-30

申请人： Mamoru Fuse

发明人： Mamoru Fuse

IPC分类号： H01L27/082 ,  H01L21/331 ,  H01L21/74 ,  H01L21/761 ,  H01L21/8228 ,  H01L29/73 ,  H01L27/02 ,  H01L27/04

CPC分类号： H01L21/74 ,  H01L21/761

摘要： A vertical PNP transistor having a large withstand voltage is disclosed. On a P-type substrate, a N-type epitaxial layer is provided. A P-type isolation region is formed in the epitaxial layer as a closed-loop to isolate a portion of the epitaxial layer from the other portions thereof. A first N-type buried layer is formed in the isolated epitaxial layer at the interface of the epitaxial layer and the semiconductor layer so as to separate the two. A second P-type buried layer is provided on top of the first buried layer. A P-type collector region is formed as a second closed-loop in the epitaxial layer enclosed within the first closed-loop. A high N-type concentration region that permits great withstand voltage is formed as a closed-loop separating the first closed-loop and the second closed-loop regions. A P-type emitter region is formed in the epitaxial layer region enclosed within the second closed-loop. Without the emitter region, the device can be used as a diode. By adding a N-type region within the emitter region, an NPNP thyristor can be obtained.

摘要翻译： 公开了具有大的耐受电压的垂直PNP晶体管。 在P型衬底上，提供了N型外延层。 在外延层中形成P型隔离区作为闭环，以将外延层的一部分与其它部分隔离。 在隔离的外延层中在外延层和半导体层的界面处形成第一N型掩埋层，以分离两者。 第二P型掩埋层设置在第一掩埋层的顶部。 在包围在第一闭环内的外延层中形成P型集电极区域作为第二闭环。 形成允许高耐受电压的高N型浓度区域形成为分离第一闭环和第二闭环区域的闭环。 在封闭在第二闭环内的外延层区域中形成P型发射极区域。 没有发射极区域，器件可以用作二极管。 通过在发射极区域内添加N型区域，可以获得NPNP晶闸管。

公开(公告)号：US4474425A

公开(公告)日：1984-10-02

申请号：US321015

申请日：1981-11-13

申请人： Kazuhisa Kaede

发明人： Kazuhisa Kaede

IPC分类号： G02B6/122 ,  G02B6/28 ,  G02B6/30 ,  G02B6/36 ,  G02B5/174

CPC分类号： G02B6/30 ,  G02B6/2808

摘要： An optical coupler formed on a substrate including a plurality of input and output guide channels and an immediate mixing guide channel connecting the input and output guide channels wherein the optical coupler comprises substantially V-shaped grooves on the substrate disposed in the ends of the input and output guide channels for receiving optical fibers.

摘要翻译： 一种形成在包括多个输入和输出引导通道的基板上的光耦合器，以及连接输入和输出引导通道的立即混合引导通道，其中光耦合器包括位于输入端的端部上的基板上的大致V形槽， 用于接收光纤的输出引导通道。

公开(公告)号：US4472646A

公开(公告)日：1984-09-18

申请号：US339796

申请日：1982-01-15

申请人： Mitsutoshi Sugawara

发明人： Mitsutoshi Sugawara

IPC分类号： H03K3/286 ,  H03K3/288

CPC分类号： H03K3/288

摘要： This invention provides a flip-flop drawing low current and occupying a small area in a semiconductor integrated circuit. The flip-flop has a first and a second transistor having their emitters grounded via a first and a second diode, respectively. The collector of the first transistor is coupled with the base of the second transistor via a third diode. Likewise, the collector of the second transistor is coupled with the base of the first transistor via a fourth diode. The output is derived from the collector of a third transistor having its base-emitter path connected in parallel with the first or second diode to form a current mirror circuit.

摘要翻译： 本发明提供一种在半导体集成电路中绘制低电流并占据小面积的触发器。 触发器具有分别经由第一和第二二极管接地的发射极的第一和第二晶体管。 第一晶体管的集电极经由第三二极管与第二晶体管的基极耦合。 类似地，第二晶体管的集电极通过第四二极管与第一晶体管的基极耦合。 输出源自具有与第一或第二二极管并联的基极 - 发射极路径的第三晶体管的集电极，以形成电流镜电路。

公开(公告)号：US4467449A

公开(公告)日：1984-08-21

申请号：US298412

申请日：1981-09-01

申请人： Mineo Hayashi

发明人： Mineo Hayashi

IPC分类号： G11C11/417 ,  G11C5/06 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C11/4094 ,  H01L21/3205 ,  H01L21/822 ,  H01L27/04 ,  G11C7/00

CPC分类号： G11C5/063 ,  G11C11/4094 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22

摘要： An improved integrated circuit in which capacitive loads can be driven at a high speed is disclosed. The circuit comprises a first and a second capacitive loads disposed separately from each other, a first switch located near the first capacitive load and adapted to drive it with a power source, a second switch located near the second capacitive load and adapted to drive it with the power source, and means for simultaneously controlling the first and second switch.

摘要翻译： 公开了可以高速驱动电容性负载的改进的集成电路。 该电路包括彼此分开设置的第一和第二容性负载，位于第一容性负载附近的第一开关，其适于用电源驱动;第二开关，位于第二容性负载附近，并适于驱动它与 电源，以及用于同时控制第一和第二开关的装置。

公开(公告)号：US4467447A

公开(公告)日：1984-08-21

申请号：US319016

申请日：1981-11-06

申请人： Toshiya Takahashi ,  Yoshikuni Sato

发明人： Toshiya Takahashi ,  Yoshikuni Sato

IPC分类号： G06F13/36 ,  G06F5/00 ,  G06F13/28 ,  G06F1/04

CPC分类号： G06F13/28

摘要： A data processing system including a central processing unit (CPU), a memory device operating on a data word length of 2 m-bits, an input/output device operating on a data word length of m bits, an m-bit register and a direct memory access (DMA) controller for transferring data words in both directions between the memory device and the input/output device independently of the CPU. A 2 m-bit bus is connected between the memory device and two m-bit buses connected to a bus switching circuit which controls the transfer of m-bit data words between the 2 m-bit bus and the register and the input/output device. A control circuit generates timing and switching signals such that, during a first bus cycle a first m-bit data word from the input/ouput device is stored in the register, and during a second bus cycle a second m-bit data word from the input/output device is transferred directly via the buses to the memory device and, also, the first m-bit data word, stored in the register, is transferred to the memory device. For transfer of a data word from the memory device to the input/output device, during a first bus cycle m bits of data are transferred directly via the buses to the input/output device and, also, the following m bits are stored in the register, and during a second bus cycle the following m bits are transferred to the input/output device.

摘要翻译： 一种数据处理系统，包括中央处理单元（CPU），以2m位数据字长度操作的存储器件，以m位数据字长度操作的输入/输出设备，m位寄存器和 直接存储器访问（DMA）控制器，用于独立于CPU在存储器件和输入/输出装置之间的两个方向上传送数据字。 一个2m位总线连接在存储器件和连接到总线切换电路的两个m位总线之间，该总线切换电路控制2m位总线与寄存器之间的m位数据字的传送以及输入/输出装置 。 控制电路产生定时和切换信号，使得在第一总线周期期间，来自输入/输出装置的第一m位数据字被存储在寄存器中，并且在第二总线周期期间，来自第二个m位数据字 输入/输出设备通过总线直接传送到存储设备，并且存储在寄存器中的第一m位数据字也被传送到存储器件。 为了将数据字从存储器件传送到输入/输出器件，在第一个总线周期期间，m位数据经由总线被直接传送到输入/输出器件，并且以下m位存储在 寄存器，并且在第二个总线周期期间，以下m位被传送到输入/输出设备。

公开(公告)号：US4467371A

公开(公告)日：1984-08-21

申请号：US484300

申请日：1983-04-18

申请人： Yosoji Kobayashi ,  Yoshitaka Kato ,  Kyoichi Tokiwa ,  Yukinori Yoneda ,  Hiroyuki Maie ,  Minoru Tamagami ,  Shoji Motohashi ,  Tatsuo Konishi ,  Shigeru Araki

发明人： Yosoji Kobayashi ,  Yoshitaka Kato ,  Kyoichi Tokiwa ,  Yukinori Yoneda ,  Hiroyuki Maie ,  Minoru Tamagami ,  Shoji Motohashi ,  Tatsuo Konishi ,  Shigeru Araki

IPC分类号： G11B27/024 ,  G11B27/32 ,  G11B27/34 ,  H04N5/782 ,  G11B27/08 ,  G11B27/10

CPC分类号： G11B27/024 ,  G11B27/32 ,  G11B27/34

摘要： For use in pre-editing a video tape, an original video tape is prepared by automatically recording successive scene numbers on a video tape in correspondence to the respective scenes being recorded on the tape. As the scenes are displayed in combination with the scene numbers, those of successive numbers preliminarily recorded on a card in one-to-one correspondence to the scene numbers are marked, which correspond to the scenes to be selected. The marked numbers are read while signals representative of the scenes and the scene numbers are reproduced from the original video tape. Each time correspondence between the marked numbers and the reproduced scene numbers is detected, scenes corresponding to the detected scene numbers are automatically transferred to another video tape to thereby complete the scene-selected video tape. The scene numbers may be recorded on the cue track to be visually displayed as successive numerals together with the corresponding scenes.

摘要翻译： 为了用于预编辑录像带，通过根据记录在磁带上的各个场景自动地在视频磁带上记录连续的场景编号来准备原始录像带。 当场景与场景号一起显示时，标记与场景号码一一对应地预先记录在卡上的连续号码的那些，其对应于要选择的场景。 读取代表场景的信号和场景编号的标记号码从原始录像带再现。 每次检测到标记号码与再现的场景号码之间的对应关系时，与检测到的场景号码相对应的场景被自动传送到另一个录像带，从而完成场景选择的录像带。 场景号码可以记录在提示轨道上，以与相应场景一起作为连续数字视觉显示。

公开(公告)号：US4467315A

公开(公告)日：1984-08-21

申请号：US934985

申请日：1978-08-18

申请人： Rikio Maruta ,  Atsushi Tomozawa

发明人： Rikio Maruta ,  Atsushi Tomozawa

IPC分类号： H03G7/00 ,  H03M7/50 ,  H04B14/04 ,  H03K13/24

CPC分类号： H03G7/007 ,  H03M7/50

摘要： A compandor converts a linear code signal consisting of a polarity bit and a plurality of absolute value bits. The polarity bit represents the polarity of each sample value of an original analog signal. The absolute value bits represent the absolute value of the sample. The compandor converts the linear code into a nonlinear code including the polarity bit, a plurality of segment bits representing the segments in a characteristic curve to which the original analog signal belongs, and mantissa bits which indicate the position of the sample value in that segment. The compandor comprises: a plurality of input terminals for receiving the linear code signal; a first read-only memory means, addressed by a first bit group among the absolute value bits for memorizing a segment bit decision rule; a second read-only memory means, addressed by a second bit group consisting of another plurality of bits among the absolute value bits and some bits in common with the first bit group for memorizing a first mantissa bit decision rule; a third read-only memory means, addressed by the first bit group, for memorizing a second mantissa bit decision rule; and means for selecting the second or third read-only memory means depending on the value of the most significant bit among the segment bits applied from the first read-only memory means.

摘要翻译： 压缩器转换由极性位和多个绝对值位组成的线性码信号。 极性位表示原始模拟信号的每个采样值的极性。 绝对值位代表样本的绝对值。 压缩器将线性代码转换为非线性代码，其包括极性位，表示原始模拟信号所属的特性曲线中的段的多个段位以及指示该段中的采样值的位置的尾数位。 该压缩器包括：用于接收线性码信号的多个输入端; 第一只读存储器装置，用于存储段位决定规则的绝对值位之中的第一位组寻址; 第二只读存储器装置，由绝对值位中的另外多个位组成的第二位组寻址，以及与用于存储第一尾数位决定规则的第一位组共同的一些位; 由第一位组寻址的用于存储第二尾数位决定规则的第三只读存储器装置; 以及用于根据从第一只读存储器装置施加的段比特中的最高有效位的值来选择第二或第三只读存储器装置的装置。

公开(公告)号：US4463419A

公开(公告)日：1984-07-31

申请号：US305234

申请日：1981-09-24

申请人： Hisao Takane

发明人： Hisao Takane

IPC分类号： G06F9/22 ,  G06F9/24 ,  G06F11/10

CPC分类号： G06F11/10 ,  G06F9/24

摘要： A microprogram control system for use in a data processor. The system has a plurality of control memories. Under the control of microinstructions stored in one control memory, a necessary microinstruction is loaded from the main memory onto the other control memory.

摘要翻译： 一种用于数据处理器的微程序控制系统。 该系统具有多个控制存储器。 在存储在一个控制存储器中的微指令的控制下，将必要的微指令从主存储器加载到另一控制存储器上。

公开(公告)号：US4462030A

公开(公告)日：1984-07-24

申请号：US329387

申请日：1981-12-10

申请人： Daisuke Ishii

发明人： Daisuke Ishii

IPC分类号： G08B21/00 ,  G08B3/10 ,  G08B7/00 ,  G08B23/00 ,  H04Q7/14 ,  G08B5/22

CPC分类号： G08B3/1025

摘要： A portable electronic apparatus has an oscillator for generating a signal. An audible annunciator has an inductance element for generating an audible annunciating signal in response to a first actuation signal of a first frequency. A light emitting means is turned on and off by counter-electromotive forces developed in the inductance element in response to one of the first actuation signal and a second actuation signal of a second frequency. A frequency divider is coupled to the audible annunciator and to the light emitting means for frequency-dividing the oscillation signal to provide the first and second actuation signals and for selectively generating one of these actuation signals in response to a control signal.

摘要翻译： 便携式电子设备具有用于产生信号的振荡器。 声音信号器具有电感元件，用于响应于第一频率的第一致动信号产生可听的信号信号。 响应于第一驱动信号和第二频率的第二致动信号之一，通过在电感元件中产生的反电动势来使发光装置接通和断开。 分频器耦合到可听报警器和发光装置，用于对振荡信号进行分频以提供第一和第二致动信号，并且响应于控制信号选择性地产生这些致动信号之一。