公开(公告)号：US08296708B1

公开(公告)日：2012-10-23

申请号：US13349584

申请日：2012-01-13

申请人： Tung-Chieh Chen ,  Bo-Wei Chen ,  Ta-Yu Kuan

发明人： Tung-Chieh Chen ,  Bo-Wei Chen ,  Ta-Yu Kuan

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5072 ,  G06F2217/06

摘要： Disclosed is a computer-implemented method to generate a placement for a plurality of device modules within an analog integrated circuit (IC) subject to a set of constraints. By building a constraint hierarchy tree according to the constraints, conflicts of constraints can be identified and resolved. Furthermore, placements can be generated based on the hierarchy tree through a bottom-to-top dimension optimization process and a top-down wire length optimization process. Furthermore, a graphical user interface can be used to display the tree, and the user can edit the tree visually and interactively.

摘要翻译： 公开了一种计算机实现的方法，用于根据一组约束来生成模拟集成电路（IC）内的多个设备模块的放置。 通过根据约束构建约束层次结构树，可以识别和解决约束冲突。 此外，可以通过底层到顶部的维度优化过程和自顶向下的线长度优化过程，基于层次树生成展示位置。 此外，可以使用图形用户界面来显示树，并且用户可以视觉和交互地编辑树。

公开(公告)号：US20120239370A1

公开(公告)日：2012-09-20

申请号：US13269085

申请日：2011-10-07

申请人： Chia-Chih Yen ,  Che-Hua Shih ,  Chun-Chi Lin

发明人： Chia-Chih Yen ,  Che-Hua Shih ,  Chun-Chi Lin

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： What-if simulation methods and systems are provided. A design coding in HDL (Hardware Description Language) and a simulation result corresponding to the design are provided. A what-if design scope and a what-if time window are received. A portion of the design is extracted from the design according to the what-if design scope, and primary input signals are determined during the extraction of the sub-design. Then, what-if simulation data is extracted from the simulation result according to the primary input signals and the what-if time window. A what-if test bench is generated according to the what-if simulation data, wherein the what-if simulation data is read, and the signal values are fed to a simulator according to the what-if test bench.

摘要翻译： 提供假设的模拟方法和系统。 提供了HDL（硬件描述语言）中的设计编码和与设计相对应的仿真结果。 接收假设设计范围和假设时间窗口。 根据设计范围从设计中提取设计的一部分，并且在提取子设计期间确定主输入信号。 然后，根据主输入信号和假设时间窗从模拟结果中提取假设的数据。 根据假设的仿真数据生成假设的试验台，其中如果假设的仿真数据被读取，并且根据假设的试验台将信号值馈送到模拟器。

公开(公告)号：US08255853B2

公开(公告)日：2012-08-28

申请号：US12756990

申请日：2010-04-08

申请人： MingYang Wang ,  Sweyyan Shei ,  Hwa Mao

发明人： MingYang Wang ,  Sweyyan Shei ,  Hwa Mao

IPC分类号： G06F17/50

CPC分类号： G06F17/5027 ,  G06F11/3652

摘要： An apparatus for circuit emulation may include a first circuit board, one or more circuit emulation resource on the first circuit board, a first interconnection interface on the first circuit board, and a second interconnection interface on the first circuit board. The first circuit board may include conductive wiring paths. The circuit emulation resource is on the first circuit board and coupled with a portion of the conductive wiring paths, with each circuit emulation resource being configured to emulate a portion of an electronic circuit by receiving input signals and producing output signals in response to the input signals. The first interconnection interface is on the first circuit board and coupled with at least a first portion of the circuit emulation resource, The first interconnection interface may be configured to couple with an interconnection interface of a second circuit board having a second group of conductive wiring paths and having a second group of circuit emulation resources. The second interconnection interface is on the first circuit board and coupled with at least a second portion of the at least one circuit emulation resource. The second interconnection interface may be configured to couple with an interconnection interface of a third circuit board having a third group of conductive wiring paths and having a third group of circuit emulation resources.

摘要翻译： 用于电路仿真的装置可以包括第一电路板，第一电路板上的一个或多个电路仿真资源，第一电路板上的第一互连接口和第一电路板上的第二互连接口。 第一电路板可以包括导电布线路径。 电路仿真资源在第一电路板上并与一部分导电布线路径耦合，每个电路仿真资源被配置为通过接收输入信号并响应输入信号产生输出信号来模拟电子电路的一部分 。 第一互连接口位于第一电路板上并与电路仿真资源的至少第一部分耦合。第一互连接口可以被配置为与具有第二组导电布线路径的第二电路板的互连接口耦合 并具有第二组电路仿真资源。 第二互连接口位于第一电路板上并与至少一个电路仿真资源的至少第二部分耦合。 第二互连接口可以被配置为与具有第三组导电布线路径并具有第三组电路仿真资源的第三电路板的互连接口耦合。

公开(公告)号：US20120137264A1

公开(公告)日：2012-05-31

申请号：US13289963

申请日：2011-11-04

申请人： Fong-Yuan Chang ,  Wei-Shun Chuang ,  Sheng-Hsiung Chen ,  Hsian-Ho Chang ,  Ruey-Shi Rau

发明人： Fong-Yuan Chang ,  Wei-Shun Chuang ,  Sheng-Hsiung Chen ,  Hsian-Ho Chang ,  Ruey-Shi Rau

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Multiple level spine routing is disclosed. In some embodiments, in response to receiving a specification of a net comprising a set of pins, a first wire for routing the net is generated, the set of pins comprising the net is partitioned into one or more groups based at least in part on a cost function, a second wire that connects to the first wire is generated for each group of the net, and a third wire that connects each pin to the second wire of its group is generated for each pin of each group of the net.

摘要翻译： 公开了多级脊柱布线。 在一些实施例中，响应于接收到包括一组引脚的网络的规范，产生用于布线网络的第一线，包括网的引脚组被至少部分地基于一个或多个 为每组网络产生连接到第一线的第二线，并且为每组网的每个针产生将每个引脚连接到其组的第二线的第三线。

公开(公告)号：US20110251836A1

公开(公告)日：2011-10-13

申请号：US12756990

申请日：2010-04-08

申请人： MingYang Wang ,  Sweyyan Shei ,  Hwa Mao

发明人： MingYang Wang ,  Sweyyan Shei ,  Hwa Mao

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5027 ,  G06F11/3652

摘要： An apparatus for circuit emulation may include a first circuit board, one or more circuit emulation resource on the first circuit board, a first interconnection interface on the first circuit board, and a second interconnection interface on the first circuit board. The first circuit board may include conductive wiring paths. The circuit emulation resource is on the first circuit board and coupled with a portion of the conductive wiring paths, with each circuit emulation resource being configured to emulate a portion of an electronic circuit by receiving input signals and producing output signals in response to the input signals. The first interconnection interface is on the first circuit board and coupled with at least a first portion of the circuit emulation resource, The first interconnection interface may be configured to couple with an interconnection interface of a second circuit board having a second group of conductive wiring paths and having a second group of circuit emulation resources. The second interconnection interface is on the first circuit board and coupled with at least a second portion of the at least one circuit emulation resource. The second interconnection interface may be configured to couple with an interconnection interface of a third circuit board having a third group of conductive wiring paths and having a third group of circuit emulation resources.

摘要翻译： 用于电路仿真的装置可以包括第一电路板，第一电路板上的一个或多个电路仿真资源，第一电路板上的第一互连接口和第一电路板上的第二互连接口。 第一电路板可以包括导电布线路径。 电路仿真资源在第一电路板上并与一部分导电布线路径耦合，每个电路仿真资源被配置为通过接收输入信号并响应输入信号产生输出信号来模拟电子电路的一部分 。 第一互连接口位于第一电路板上并与电路仿真资源的至少第一部分耦合。第一互连接口可以被配置为与具有第二组导电布线路径的第二电路板的互连接口耦合 并具有第二组电路仿真资源。 第二互连接口位于第一电路板上并与至少一个电路仿真资源的至少第二部分耦合。 第二互连接口可以被配置为与具有第三组导电布线路径并具有第三组电路仿真资源的第三电路板的互连接口耦合。

公开(公告)号：US20110238397A1

公开(公告)日：2011-09-29

申请号：US13047007

申请日：2011-03-14

申请人： Yung Chuan Chen ,  I-Liang Lin ,  Li-Chi Chang ,  Bindesh Patel

发明人： Yung Chuan Chen ,  I-Liang Lin ,  Li-Chi Chang ,  Bindesh Patel

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F11/3672

摘要： Methods and apparatus for recording and visualizing transactions of a test bench simulation are disclosed. Transaction-specific data generated from a test bench simulation may be displayed in a sequence diagram view to provide a view of the transactions arranged sequentially in time.

摘要翻译： 公开了用于记录和可视化测试台模拟的交易的方法和装置。 可以在序列图视图中显示从测试台仿真生成的特定于事务的数据，以提供按时间顺序排列的事务的视图。

公开(公告)号：US20110202894A1

公开(公告)日：2011-08-18

申请号：US13025809

申请日：2011-02-11

申请人： Ying-Tsai Chang ,  Hwa Mao ,  Swey-Yan Shei ,  Ming-Yang Wang ,  Yu-Chin Hsu

发明人： Ying-Tsai Chang ,  Hwa Mao ,  Swey-Yan Shei ,  Ming-Yang Wang ,  Yu-Chin Hsu

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5027

摘要： Methods and systems for testing a prototype, the method including receiving, at a first interface component, a configuration parameter associated with a configured image representative of at least a portion of a user design and an associated verification module. The method further includes, sending, using the first interface component, the configured image to a device. A second interface component may be configured to send timing and control information to the verification module based on at least one of the configuration image and runtime control information received from the first interface component. In response to receiving the timing and control information from the second interface component, the verification module may control the device and/or monitor the device state of at least a portion of the user design.

摘要翻译： 用于测试原型的方法和系统，所述方法包括在第一接口部件处接收与代表用户设计的至少一部分的配置图像相关联的配置参数和相关联的验证模块。 该方法还包括：使用第一接口组件将配置的图像发送到设备。 第二接口部件可以被配置为基于从第一接口部件接收到的配置图像和运行时间控制信息中的至少一个来向定时模块发送定时和控制信息。 响应于从第二接口部件接收定时和控制信息，验证模块可以控制设备和/或监视用户设计的至少一部分的设备状态。

公开(公告)号：US07603640B2

公开(公告)日：2009-10-13

申请号：US11550487

申请日：2006-10-18

申请人： Shyh-Chang Lin ,  Tung-Chieh Chen ,  Yao-Wen Chang

发明人： Shyh-Chang Lin ,  Tung-Chieh Chen ,  Yao-Wen Chang

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： To generate a floorplan for an integrated circuit to be formed by a collection of modules interconnected by nets, the floorspace to be occupied by the integrated circuit is partitioned into regions and all of the modules are allocated among those regions. The regions are then iteratively partitioning into smaller progressively smaller regions with modules previously allocated any partitioned region allocated among the regions into which it was partitioned, until each region of the floorplan has been allocated no more than a predetermined maximum number of modules. A separate floorplan is then generated for each region. Neighboring regions are then iteratively merged to create progressively larger regions, until only a single region remains, wherein upon merging any neighboring regions to form a larger merged region, the floorplans of the neighboring regions are merged and refined to create a floorplan for the merged region.

摘要翻译： 为了生成由网络互连的模块的集合形成的集成电路的平面图，将由集成电路占据的楼层空间划分为区域，并且所有模块都被分配在这些区域中。 然后将区域迭代地划分成更小的逐渐变小的区域，其中模块先前分配了在其被分割的区域中分配的任何分区，直到布局图的每个区域已经被分配不超过预定的最大数量的模块。 然后为每个区域生成单独的平面图。 然后迭代地合并相邻区域以创建逐渐更大的区域，直到仅剩下一个区域，其中在合并任何相邻区域以形成更大的合并区域时，相邻区域的平面图被合并和细化以创建合并区域的平面图 。

公开(公告)号：US20090187394A1

公开(公告)日：2009-07-23

申请号：US12015779

申请日：2008-01-17

申请人： Kuo-Ching Lin ,  Nan-Ting Yeh ,  Kuen-Yang Tsai

发明人： Kuo-Ching Lin ,  Nan-Ting Yeh ,  Kuen-Yang Tsai

IPC分类号： G06G7/48

CPC分类号： G06F17/5022

摘要： A computer-based simulation process executes a checkpoint operation while simulating behavior of an electronic circuit by forking an active checkpoint process having the same state as the original simulation process. While simulation time for the simulation process continues to increase after executing the checkpoint operation, simulation time for the checkpoint process remains unchanged so that the checkpoint process remains in the state of the simulation at the simulation time it executed the checkpoint operation (the “checkpoint time”). When the checkpoint process subsequently receives a request to resume simulating the circuit, it forks a new simulation process that mimics the original simulation process as of checkpoint time, and the new simulation process then begins to advance its simulation time, thereby enabling it to re-simulate behavior of the electronic circuit previously simulated by the original simulation process starting from the checkpoint time.

摘要翻译： 基于计算机的模拟处理通过分析具有与原始模拟处理相同的状态的主动检查点处理来模拟电子电路的行为来执行检查点操作。 在执行检查点操作之后，仿真过程的仿真时间持续增加，检查点处理的仿真时间保持不变，使得检查点进程在执行检查点操作的模拟时间（“检查点时间”）处于模拟状态 “）。 当检查点处理随后接收到恢复模拟电路的请求时，它将从检查点时间起叉一个模拟原始模拟过程的新模拟过程，然后新的仿真过程开始提高其仿真时间， 模拟从原始模拟过程模拟的电子电路的行为，从检查点时间开始。

公开(公告)号：US20090031269A1

公开(公告)日：2009-01-29

申请号：US12168288

申请日：2008-07-07

申请人： Tung-Chieh Chen ,  Che-Wei Jiang

发明人： Tung-Chieh Chen ,  Che-Wei Jiang

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A placer produces a global placement plan specifying positions of cell instances to be interconnected by nets within an integrated circuit (IC) by initially clusterizing cell instances to form a pyramidal hierarchy of blocks and generating an initial global placement plan specifying a position of each block at a highest level of the hierarchy. The placer then declusterizes the global placement plan by replacing the highest level blocks with their component blocks and then improves the routability of the global placement plan by iteratively moving specified block positions in directions and by distances dynamically determined by analyzing the global placement plan and an objective function having a total wirelength term and having a bin density term reflecting density of blocks in specified areas (bins) of the IC. The placer iteratively repeats the declusterization and routability improvement process until the global placement plan specifies positions of all blocks residing at the lowest level of the hierarchy, with weighting of the bin density term adjusted when necessary during each iteration of the routability improvement process to provide sufficient white space in each bin. The placer employs a look-ahead legalization technique to move low level blocks to legal positions during later iterations of the plan improvement process.

摘要翻译： 放样器通过初始地将单元实例聚类以形成块的锥体层级并且产生指定每个块的位置的初始全局放置计划来产生通过集成电路（IC）中的网互连的单元实例的位置的全局布局计划 层次结构的最高级别。 然后，放样器通过用其组件块替换最高级别块来对全局布局计划进行解聚集，然后通过迭代地移动指定的块位置，通过分析全局布局计划和目标而动态确定的距离来改进全局布局计划的可布线性 功能具有总线长度项，并且具有反映IC的特定区域（箱）中块的密度的bin密度项。 放样器迭代地重复去分散化和可路由性改进过程，直到全局放置计划指定驻留在层次结构的最低级的所有块的位置，在可行性改进过程的每次迭代期间必要时调整二进制密度项的权重以提供足够的 每个垃圾桶的空白。 在稍后的计划改进过程中，Placer采用了先行合法化技术将低级别块移动到合法位置。