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公开(公告)号：US10236842B2
公开(公告)日：2019-03-19
申请号：US15393485
申请日：2016-12-29
Inventor： Vratislav Michal , Michel Ayraud
Abstract: A circuit includes an amplifier having a first power terminal configured to be coupled to a supply voltage and a second power terminal configured to be coupled to a reference potential. The circuit further includes a first impedance element coupled between a first input terminal of the amplifier and a first output terminal of the amplifier. The circuit additionally includes a second impedance element coupled between the first input terminal and the reference potential. The amplifier is configured to output a first voltage at a second output terminal of the amplifier in response to the supply voltage being greater than an output voltage at the first output terminal of the amplifier. The amplifier is further configured to output a second voltage at the second output terminal of the amplifier in response to the supply voltage being less than the output voltage at the first output terminal of the amplifier.
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公开(公告)号：US20180367171A1
公开(公告)日：2018-12-20
申请号：US16003623
申请日：2018-06-08
Applicant: STMicroelectronics (Alps) SAS
Inventor： Herve JACOB
IPC: H04B1/04
CPC classification number: H04B1/04 , H03F1/223 , H03F1/3247 , H03F3/195 , H03F3/245 , H03F3/45376 , H03F2200/204 , H03F2200/207 , H03F2200/534 , H03F2200/537 , H03F2200/555 , H03F2203/45394 , H03F2203/45544 , H03F2203/45548 , H03F2203/45594 , H03F2203/45604 , H04B2001/0425
Abstract: A transmission chain receives an incident signal to be transmitted having a first power and a first bandwidth. A first modulator frequency shifts a first signal derived from the incident signal to generate a first shifted signal at a modulation output. A power amplifier coupled to the modulation output amplifies an intermediate signal to generate an amplified output signal. A predistortion-signal-generating circuit generates, from the incident signal and from the amplified output signal in a second bandwidth that is larger than the first bandwidth, a predistortion signal having a second power lower than the first power. A second modulator frequency shifts a second signal derived from the predistortion signal to generate a second shifted signal for combination with the first shifted signal at said modulation output to produce the intermediate signal.
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43.发明申请公开(公告)号：US20180309187A1
公开(公告)日：2018-10-25
申请号：US16017611
申请日：2018-06-25
Inventor： David Auchere , Laurent Marechal , Yvon Imbs , Laurent Schwarz
IPC: H01Q1/22 , H01L23/31 , H01L21/56 , H01L23/498 , H01L21/48 , H01L23/66 , H01L21/3105
Abstract: An electronic device includes a support plate having a mounting face and an electrical connection network. An integrated circuit chip is mounted on the mounting face and linked to the electrical connection network. An encapsulation block embeds the integrated circuit chip. An additional element made of an electrically conductive material is at least partly embedded within the encapsulation block. The additional conductive element has a main portion extending parallel to the support plate and has a secondary portion that is linked electrically to the integrated circuit chip. An opening is formed in the encapsulation block, and the secondary portion extends into that opening to make the electrical link. The additional conductive element may be an antenna.
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公开(公告)号：US10067200B2
公开(公告)日：2018-09-04
申请号：US15076955
申请日：2016-03-22
Applicant: STMicroelectronics (Alps) SAS
Inventor： Bruno Leduc , Pascal Bernon , Stephane Clin
Abstract: A circuit includes, in series between a first terminal and a second terminal of application of a power supply voltage, and first and second branches. The first branch includes a first transistor and a first current source coupled to the first transistor. The second branch includes a resistive element, a second transistor coupled to the resistive element and forming a current mirror with the first transistor and a second current source coupled to the second transistor. The resistive element conditions a threshold of detection of a variation of the power supply voltage.
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公开(公告)号：US09933797B1
公开(公告)日：2018-04-03
申请号：US15495504
申请日：2017-04-24
Applicant: STMicroelectronics (Alps) SAS
Inventor： Frederic Lebon
Abstract: An integrated electronic device includes a core having a first terminal and a second terminal. The core includes a first branch with a first diode-connected bipolar transistor coupled in series to a first resistor between the first terminal and a reference terminal intended to be supplied with a reference voltage, and a second branch with a second diode-connected bipolar transistor coupled between the second terminal and the reference terminal. The second diode-connected bipolar transistor has a current density higher than the first diode-connected bipolar transistor. The core also includes a first resistive network coupled between a base of the first diode-connected bipolar transistor and the reference terminal. An equalizer is configured to equalize potentials of the first terminal and of the second terminal and a voltage generator is coupled to the first and second terminals of the core and configured to generate the bandgap voltage.
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Patent Agency Ranking
公开(公告)号：US09892877B2
公开(公告)日：2018-02-13
申请号：US14657991
申请日：2015-03-13
Applicant: STMicroelectronics (Alps) SAS
Inventor： Vratislav Michal , Denis Cottin
CPC classification number: H01H47/00 , H03K17/167 , H03K17/30 , H03K2017/307 , Y10T307/76
Abstract: A circuit including: a plurality of first switches connected in parallel between a first terminal and a second terminal; and a control circuit capable of implementing the following steps at each period of a clock signal: comparing the voltage between the first and second terminals with a reference voltage; if the voltage between the first and second terminals is greater than the reference voltage, turning on one of the first switches without modifying the state of the other switches; and if the voltage between the first and second terminals is smaller than the reference voltage, turning off one of the first switches without modifying the state of the other switches.
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公开(公告)号：US09847798B2
公开(公告)日：2017-12-19
申请号：US14961996
申请日：2015-12-08
Inventor： Julien Saade , Abdelaziz Goulahsen
CPC classification number: H04B1/04 , G06F13/4282 , H04L25/4908
Abstract: The invention relates to a method for serial data transmission, comprising the steps consisting in computing the running disparity (RD) of a bit stream that is being transmitted; when the running disparity reaches a threshold (T), computing a point disparity on a subsequent frame (S) of the stream; if the point disparity has the same sign as the threshold, inverting the states of the bits of the frame in the transmitted bit stream; and inserting into the transmitted bit stream a polarity bit having a state signalling the inversion.
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公开(公告)号：US09813655B2
公开(公告)日：2017-11-07
申请号：US15237103
申请日：2016-08-15
Applicant: STMicroelectronics (Alps) SAS
Inventor： Serge Hembert
CPC classification number: H04N5/44 , G09G5/006 , G09G2340/02 , G09G2370/20 , G09G2370/22 , H04R2420/05
Abstract: A video and/or audio decoder provided with a first terminal for supplying an analog audio and/or video signal, including: a first circuit capable of supplying a digital signal which is an image of said analog signal; a digital-to-analog converter capable of receiving as an input said digital signal; an amplifier coupling a second output terminal of the digital-to-analog converter to the first terminal; and a second circuit capable of comparing a signal representative of the voltage or current level on the first terminal with a reference signal, and of deducing therefrom whether the first terminal is connected or not to an analog input terminal of a video signal display and/or audio signal playing device.
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公开(公告)号：US09698183B2
公开(公告)日：2017-07-04
申请号：US14744482
申请日：2015-06-19
Inventor： Nicolas Moeneclaey , Julien-Marc Roux , Jerome Bourgoin
IPC: H04N5/374 , H01L27/146 , H04N5/378 , H04N5/367 , H04N17/00 , H04N5/3745
CPC classification number: H01L27/14612 , H01L27/14643 , H04N5/367 , H04N5/374 , H04N5/3742 , H04N5/3745 , H04N5/378 , H04N17/002
Abstract: A CMOS image sensor including: an array of M×N pixels, the pixels of a same column being connected to a same output track, each pixel including a photodiode, a sense node, a transfer transistor, a reset transistor, and a read circuit; and a test circuit including an assembly of N elementary reference cells respectively connected to the N output tracks of the sensor, each cell including a resistor, a sense node, a transfer transistor, a reset transistor, and a read circuit, the N resistors being series-connected between first and second nodes of application of a reference voltage.
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公开(公告)号：US12229253B2
公开(公告)日：2025-02-18
申请号：US17340164
申请日：2021-06-07
Inventor： Asif Rashid Zargar , Gilles Eyzat , Charul Jain
IPC: G06F21/55
Abstract: A system on a chip comprising a set of one-time programmable memory elements that comprises a first valid configuration; a second valid configuration; and a plurality of invalid configurations. The system on a chip also comprises a programming indicator initially comprising a first value and configured to be permanently set to a second value. The system on a chip further comprises a decoder circuit in communication with the set of one-time programmable memory elements to determine whether the set of one-time programmable memory elements is in the first valid configuration, the second valid configuration, or any one of the plurality of invalid configurations. The decoder circuit generates a threat-detection signal when the set of one-time programmable memory elements is in any of the plurality of invalid configurations when the programming indicator is permanently set to the second value.
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