公开(公告)号：US08000165B2

公开(公告)日：2011-08-16

申请号：US12207011

申请日：2008-09-09

Applicant: Changho Jung ,  Nan Chen ,  Zhiqin Chen

Inventor： Changho Jung ,  Nan Chen ,  Zhiqin Chen

IPC: G11C8/00

CPC classification number: G11C7/22 ,  G11C7/225 ,  H03K3/0372

Abstract: A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the logic gates. The cross-coupled logic circuit is coupled to an input for accepting a clock signal. The memory device also includes a clock driver operable to generate a clock signal from the output of the cross-coupled logic circuit. A feedback loop from the clock signal to the cross-coupled logic circuit controls the cross-coupled logic circuit. A buffer circuit including a tri-state inverter is coupled to the clock signal to maintain the clock signal while avoiding contention with the clock generator. The memory device is enabled by a chip select signal.

公开(公告)号：US20110185219A1

公开(公告)日：2011-07-28

申请号：US13013157

申请日：2011-01-25

Applicant: Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

Inventor： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

IPC: G06F1/08

CPC classification number: G11C5/063 ,  G06F1/10 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4076 ,  G11C2207/105

Abstract: A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

公开(公告)号：US20110032787A1

公开(公告)日：2011-02-10

申请号：US12851718

申请日：2010-08-06

Applicant: Hyoung-Seok Kim ,  Kwan-Yong Jin

Inventor： Hyoung-Seok Kim ,  Kwan-Yong Jin

IPC: G11C8/18

CPC classification number: G11C8/18 ,  G11C7/22 ,  G11C7/225 ,  G11C8/06

Abstract: An input buffer circuit includes a logic unit, a clock enable buffer, and a clock buffer. The logic unit is configured to receive a clock signal and a clock enable signal, and to output a decision signal indicative of whether the clock signal is normally input, where the decision signal is activated when the clock signal is normally input. The clock enable buffer is configured to buffer the clock enable signal and to activate an internal clock enable signal, in response to an activation of the decision signal. The clock buffer is configured to buffer the clock signal and to output an internal clock signal, in response to an activation of the internal clock enable signal.

Abstract translation: 输入缓冲电路包括逻辑单元，时钟使能缓冲器和时钟缓冲器。 逻辑单元被配置为接收时钟信号和时钟使能信号，并且输出指示时钟信号是否正常输入的判定信号，其中当正常输入时钟信号时，决定信号被激活。 响应于决定信号的激活，时钟使能缓冲器被配置为缓冲时钟使能信号并激活内部时钟使能信号。 响应于内部时钟使能信号的激活，时钟缓冲器被配置为缓冲时钟信号并输出​​内部时钟信号。

公开(公告)号：US20100329062A1

公开(公告)日：2010-12-30

申请号：US12492364

申请日：2009-06-26

Applicant: Brian J. Campbell ,  Greg M. Hess ,  Hang Huang

Inventor： Brian J. Campbell ,  Greg M. Hess ,  Hang Huang

IPC: G11C5/14 ,  G11C7/00

CPC classification number: G11C7/04 ,  G11C7/12 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225

Abstract: In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, and particularly there may be one or more level shifters that generate precharge enable signals to control the bit line precharge circuits. The level shifters for the bit line precharge circuits may also be controlled, during periods of time that the memory circuit is idle, by an input control signal (FloatBL herein). If the FloatBL signal is asserted, the bit line precharge circuits may be disabled to float the bit lines. In some embodiments, the FloatBL signal may also disable bit line bit line hold circuits on the bit lines. In some embodiments, when the memory circuit is exiting an idle state, the bit line precharge circuits may be enabled in a staggered fashion.

Abstract translation: 在一个实施例中，集成电路包括逻辑电路和包括多个位线和位线预充电电路的存储器电路。 存储电路可以包括用于由逻辑电路输入产生的控制信号的电平移位器，特别地，可以有一个或多个电平移位器产生预充电使能信号以控制位线预充电电路。 用于位线预充电电路的电平移位器也可以通过输入控制信号（这里为FloatBL）在存储器电路空闲的时间段期间被控制。 如果FloatBL信号有效，则可能禁止位线预充电电路浮动位线。 在一些实施例中，FloatBL信号还可以禁止位线上的位线位线保持电路。 在一些实施例中，当存储器电路退出空闲状态时，位线预充电电路可以以交错方式启用。

公开(公告)号：US07705634B2

公开(公告)日：2010-04-27

申请号：US11964792

申请日：2007-12-27

Applicant: Hong-Sok Choi

Inventor： Hong-Sok Choi

IPC: H03K5/22

CPC classification number: G11C5/14 ,  G11C7/22 ,  G11C7/225

Abstract: An input circuit is disclosed. The input circuit can include a cross voltage generating block that can be configured to perform charge-sharing on a pair of input signals whose phases are opposite to each other and generate a cross voltage, and an input buffer block that can be configured to buffer the pair of input signals at a voltage level corresponding to a voltage level of the cross voltage and generate an output signal.

Abstract translation: 公开了一种输入电路。 输入电路可以包括交叉电压产生块，其可以被配置为在相位彼此相反并产生交叉电压的一对输入信号上执行电荷共享，以及输入缓冲器块，其可被配置为缓冲 一对输入信号处于与交叉电压的电压电平对应的电压电平并产生输出信号。

公开(公告)号：US20090323436A1

公开(公告)日：2009-12-31

申请号：US12313102

申请日：2008-11-17

Applicant: Sang Kwon Lee

Inventor： Sang Kwon Lee

IPC: G11C7/00 ,  G11C8/00 ,  G11C8/18

CPC classification number: G11C11/406 ,  G11C7/222 ,  G11C7/225 ,  G11C11/40615 ,  G11C11/4076 ,  G11C2211/4065

Abstract: A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable signals based on an external clock enable signal in response to the flag signal, and a chip select signal buffer which generates an internal chip select signal based on an external chip select signal in response to the flag signal.

Abstract translation: 半导体存储器件的刷新信号产生电路包括一个标志信号发生器，该标志信号发生器响应于刷新信号和一个预充电信号产生一个标志信号;一个时钟使能信号缓冲器，其基于外部时钟使能产生第一和第二缓冲器使能信号 响应于标志信号的信号，以及片选信号缓冲器，其响应于标志信号，基于外部片选信号产生内部片选信号。

公开(公告)号：US20090119472A1

公开(公告)日：2009-05-07

申请号：US12262124

申请日：2008-10-30

Applicant: Kazimierz Szczypinski

Inventor： Kazimierz Szczypinski

IPC: G06F12/00 ,  G06F1/08 ,  G06F1/04

CPC classification number: G11C7/1027 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/225

Abstract: Embodiments of the invention relate to a control circuit comprising a clock signal connection for receiving a system clock signal, a write signal connection for receiving a write signal, and a write control circuit for executing write commands, wherein the write control circuit is designed to start executing a write command when a write signal is applied to the write signal connection during an edge of the system clock signal.

Abstract translation: 本发明的实施例涉及包括用于接收系统时钟信号的时钟信号连接，用于接收写信号的写信号连接和用于执行写命令的写控制电路的控制电路，其中写控制电路被设计为开始 当在系统时钟信号的边沿期间写入信号被施加到写入信号连接时执行写入命令。

公开(公告)号：US20080279031A1

公开(公告)日：2008-11-13

申请号：US11959358

申请日：2007-12-18

Applicant: Tae Heui Kwon ,  Jae Boum Park

Inventor： Tae Heui Kwon ,  Jae Boum Park

IPC: G11C5/14 ,  G11C7/10

CPC classification number: G11C5/147 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/225 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2227

Abstract: A semiconductor integrated circuit includes a first buffer and a second buffer having different operational timing, a first voltage power supply for generating a first power supply voltage supplied to the first buffer in accordance with the operational timing of the first buffer, and a second voltage power supply for generating a second power supply voltage supplied to the second buffer in accordance with the operational timing of the second buffer.

Abstract translation: 半导体集成电路包括具有不同工作时序的第一缓冲器和第二缓冲器，用于根据第一缓冲器的操作定时产生提供给第一缓冲器的第一电源电压的第一电压电源和第二电压电源 用于根据第二缓冲器的操作定时产生提供给第二缓冲器的第二电源电压。

公开(公告)号：US20080170461A1

公开(公告)日：2008-07-17

申请号：US11878250

申请日：2007-07-23

Applicant: Kie Bong Ku

Inventor： Kie Bong Ku

IPC: G11C8/00

CPC classification number: G11C11/4093 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4076

Abstract: A semiconductor memory apparatus includes a rising output data generator that generates rising output data from rising data in response to a rising clock and a rising output enable signal. A rising data output buffer buffers the rising output data. A falling output data generator generates falling output data from falling data in response to a falling clock and a falling output enable signal. A falling data output buffer buffers the falling output data.

Abstract translation: 半导体存储装置包括上升输出数据发生器，其响应于上升时钟和上升输出使能信号从上升数据产生上升的输出数据。 上升的数据输出缓冲器缓冲上升的输出数据。 下降输出数据发生器响应于下降时钟和下降的输出使能信号从下降的数据产生下降的输出数据。 下降的数据输出缓冲器缓冲下降的输出数据。

公开(公告)号：US07245554B2

公开(公告)日：2007-07-17

申请号：US11352393

申请日：2006-02-13

Applicant: Heiko Fibranz

Inventor： Heiko Fibranz

IPC: G11C8/00

CPC classification number: G11C7/22 ,  G11C7/225 ,  G11C11/4076

Abstract: An integrated semiconductor memory device includes a first input amplifier which, compared with a second input amplifier, has a lower sensitivity with regard to level fluctuations of its respective input signal. A control circuit drives a controllable switch in such a way that when a noisy clock signal is applied to the integrated semiconductor memory device, the less sensitive input amplifier is used for generating an internal clock signal. If, by contrast, a lower-noise clock signal is applied to the integrated semiconductor memory device, the control circuit drives the controllable switch in such a way that the more sensitive input amplifier is used for generating the internal clock signal. The changeover of the controllable switch is effected after evaluation of a bit sequence applied to a further input terminal of the integrated semiconductor memory device.

Abstract translation: 集成半导体存储器件包括与第二输入放大器相比相对于其相应输入信号的电平波动具有较低灵敏度的第一输入放大器。 控制电路驱动可控开关，使得当噪声时钟信号被施加到集成半导体存储器件时，较不灵敏的输入放大器用于产生内部时钟信号。 相比之下，如果将低噪声时钟信号施加到集成半导体存储器件，则控制电路以更灵敏的输入放大器用于产生内部时钟信号的方式驱动可控开关。 可控开关的切换在评估施加到集成半导体存储器件的另一个输入端子的位序列之后进行。