公开(公告)号：US06762630B2

公开(公告)日：2004-07-13

申请号：US10033123

申请日：2001-10-22

申请人： Heiko Fibranz ,  Eckehard Plaettner

发明人： Heiko Fibranz ,  Eckehard Plaettner

IPC分类号： H03L700

CPC分类号： G11C7/1006 ,  G11C2207/104 ,  H03K5/135

摘要： An integrated circuit has a synchronous circuit and an asynchronous circuit. A clock-controlled input register circuit and an output register circuit for storing data are each connected to the synchronous circuit and the asynchronous circuit. Data are transferred from the synchronous circuit into the input register circuit, from where they are transferred into the asynchronous circuit and processed in the asynchronous circuit. Processed data are transferred into the output register circuit. A sequence controller generates a respective control clock signal for the register circuits in a manner dependent on the data processing duration of the asynchronous circuit. This enables a high data throughput between the synchronous circuit and the asynchronous circuit independently of a clock frequency of the synchronous circuit.

摘要翻译： 集成电路具有同步电路和异步电路。 时钟控制输入寄存器电路和用于存储数据的输出寄存器电路各自连接到同步电路和异步电路。 数据从同步电路传送到输入寄存器电路，从它们被传送到异步电路并在异步电路中进行处理。 处理的数据被传送到输出寄存器电路。 序列控制器以取决于异步电路的数据处理持续时间的方式为寄存器电路产生相应的控制时钟信号。 这使得独立于同步电路的时钟频率的同步电路和异步电路之间的高数据吞吐量。

公开(公告)号：US5875450A

公开(公告)日：1999-02-23

申请号：US795079

申请日：1997-02-05

申请人： Robert Reiner ,  Joachim Weitzel ,  Heiko Fibranz ,  Gerhard Schraud ,  Walter Strubel ,  Dominik Berger ,  Wolfgang Eber ,  Gerald Holweg

发明人： Robert Reiner ,  Joachim Weitzel ,  Heiko Fibranz ,  Gerhard Schraud ,  Walter Strubel ,  Dominik Berger ,  Wolfgang Eber ,  Gerald Holweg

IPC分类号： G06K17/00 ,  G06K19/07 ,  G06K19/077 ,  G06F13/00

CPC分类号： G06K19/0723 ,  G06K19/077

摘要： A device for processing and storing data, in particular a chip card, includes a first interface with contacts and a second contactless interface for receiving energy or power from and for communication with a terminal device. A first controllable switching device connects either the first or the second interface to a non-volatile semiconductor memory through address, data and control lines. A logic circuit drives the first controllable switching device. A second controllable switching device disposed between the first controllable switching device and the memory can be driven at least by the logic circuit and an address signal present on the address lines.

摘要翻译： 一种用于处理和存储数据的设备，特别是芯片卡，包括具有触点的第一接口和用于从终端设备接收能力或用于与终端设备通信的第二非接触接口。 第一可控开关器件通过地址，数据和控制线将第一或第二接口连接到非易失性半导体存储器。 逻辑电路驱动第一可控开关装置。 设置在第一可控开关装置和存储器之间的第二可控开关装置可以至少由逻辑电路和存在于地址线上的地址信号驱动。

公开(公告)号：US07245554B2

公开(公告)日：2007-07-17

申请号：US11352393

申请日：2006-02-13

申请人： Heiko Fibranz

发明人： Heiko Fibranz

IPC分类号： G11C8/00

CPC分类号： G11C7/22 ,  G11C7/225 ,  G11C11/4076

摘要： An integrated semiconductor memory device includes a first input amplifier which, compared with a second input amplifier, has a lower sensitivity with regard to level fluctuations of its respective input signal. A control circuit drives a controllable switch in such a way that when a noisy clock signal is applied to the integrated semiconductor memory device, the less sensitive input amplifier is used for generating an internal clock signal. If, by contrast, a lower-noise clock signal is applied to the integrated semiconductor memory device, the control circuit drives the controllable switch in such a way that the more sensitive input amplifier is used for generating the internal clock signal. The changeover of the controllable switch is effected after evaluation of a bit sequence applied to a further input terminal of the integrated semiconductor memory device.

摘要翻译： 集成半导体存储器件包括与第二输入放大器相比相对于其相应输入信号的电平波动具有较低灵敏度的第一输入放大器。 控制电路驱动可控开关，使得当噪声时钟信号被施加到集成半导体存储器件时，较不灵敏的输入放大器用于产生内部时钟信号。 相比之下，如果将低噪声时钟信号施加到集成半导体存储器件，则控制电路以更灵敏的输入放大器用于产生内部时钟信号的方式驱动可控开关。 可控开关的切换在评估施加到集成半导体存储器件的另一个输入端子的位序列之后进行。

公开(公告)号：US06744304B2

公开(公告)日：2004-06-01

申请号：US10234078

申请日：2002-09-03

申请人： Jens Egerer ,  Heiko Fibranz ,  Eckehard Plaettner

发明人： Jens Egerer ,  Heiko Fibranz ,  Eckehard Plaettner

IPC分类号： G05F322

CPC分类号： G05F3/225

摘要： An electronic circuit for generating an output voltage has a defined temperature dependence, a bandgap circuit for generating a defined temperature-constant voltage and a temperature-dependent current with a defined temperature dependence, and a conversion circuit for generating the output voltage from the temperature-dependent current and the temperature-constant voltage. The conversion circuit has a first resistor at whose first terminal the temperature-constant voltage is applied, and whose second terminal is connected to a first terminal of a second resistor. The second terminal of the second resistor is connected to a supply voltage potential, and a first terminal of a third resistor is connected to the second terminal of the first resistor. The temperature-dependent current is supplied to a second terminal of the third resistor, and it being possible to tap the output voltage at the second terminal of the third resistor.

摘要翻译： 用于产生输出电压的电子电路具有确定的温度依赖性，用于产生限定的温度恒定电压的带隙电路和具有确定的温度依赖性的依赖于温度的电流，以及用于从温度依赖性产生输出电压的转换电路， 依赖电流和温度恒定电压。 转换电路具有第一电阻器，其第一端子施加温度恒定电压，并且其第二端子连接到第二电阻器的第一端子。 第二电阻器的第二端子连接到电源电压电位，第三电阻器的第一端子连接到第一电阻器的第二端子。 温度相关电流被提供给第三电阻器的第二端子，并且可以抽出第三电阻器的第二端子处的输出电压。

公开(公告)号：US20090323414A1

公开(公告)日：2009-12-31

申请号：US12164251

申请日：2008-06-30

申请人： Heiko Fibranz ,  Paul Schmoelz

发明人： Heiko Fibranz ,  Paul Schmoelz

IPC分类号： G11C16/04 ,  G11C7/00 ,  G11C11/00

CPC分类号： G11C16/0475 ,  G11C7/1006 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C16/0416 ,  G11C2211/5641 ,  G11C2213/79

摘要： In one aspect a method of storing data in an integrated circuit may include identifying a group of storage sites from a plurality of storage sites; selecting a plurality of storage levels, each storage level being assignable to a storage site in the group of storage sites; and assigning a unique storage level to each of the storage sites in the group of storage sites, each unique storage level assigned from the plurality of storage levels.

摘要翻译： 一方面，在集成电路中存储数据的方法可以包括从多个存储位置识别一组存储位置; 选择多个存储级别，每个存储级别可分配给存储站点组中的存储站点; 以及向所述存储站点组中的每个存储站点分配唯一存储级别，每个所述存储级别从所述多个存储级别分配的每个唯一存储级别。

公开(公告)号：US5999713A

公开(公告)日：1999-12-07

申请号：US702903

申请日：1996-08-26

申请人： Robert Reiner ,  Gerhard Schraud ,  Walter Strubel ,  Heiko Fibranz ,  Joachim Weitzel ,  Dominik Berger ,  Wolfgang Eber ,  Gerald Holweg

发明人： Robert Reiner ,  Gerhard Schraud ,  Walter Strubel ,  Heiko Fibranz ,  Joachim Weitzel ,  Dominik Berger ,  Wolfgang Eber ,  Gerald Holweg

IPC分类号： G06F12/00 ,  G06K7/00 ,  G06K17/00 ,  G06K19/07 ,  G06K19/073 ,  G06F13/00

CPC分类号： G06K19/07769 ,  G06K19/07 ,  G06K19/0701 ,  G06K19/0723 ,  G06K7/0008

摘要： A chip card includes a semiconductor chip that contains at least one memory. In order to supply energy to the chip and to provide for bi-directional data transmission from and to the chip, both contacts and a device for contactless data transmission are provided. A triggerable switch device which is provided on the chip connects the memory either to the contacts or to the device for contactless data transmission as a function of a state of an output signal of a logic circuit connected to at least a voltage supply contact. The switch device assumes a position of repose when it is not triggered and in that position it connects the memory to the device for contactless data transmission, while only upon application of a voltage to the supply voltage contact, triggered by the logic circuit, does it connect the contacts to the memory.

摘要翻译： 芯片卡包括包含至少一个存储器的半导体芯片。 为了向芯片提供能量并提供从芯片到芯片的双向数据传输，提供了两个触点和用于非接触式数据传输的装置。 设置在芯片上的可触发开关装置将存储器连接到触点或用于非接触式数据传输的装置，作为连接至少电压供应触点的逻辑电路的输出信号的状态的函数。 开关装置在不被触发时呈现静止位置，并且在该位置，它将存储器连接到用于非接触式数据传输的装置，而只有在由逻辑电路触发的电源电压触点施加电压时， 将联系人连接到内存。

公开(公告)号：US20060197553A1

公开(公告)日：2006-09-07

申请号：US11352393

申请日：2006-02-13

申请人： Heiko Fibranz

发明人： Heiko Fibranz

IPC分类号： H03K19/177

CPC分类号： G11C7/22 ,  G11C7/225 ,  G11C11/4076

摘要： An integrated semiconductor memory device includes a first input amplifier which, compared with a second input amplifier, has a lower sensitivity with regard to level fluctuations of its respective input signal. A control circuit drives a controllable switch in such a way that when a noisy clock signal is applied to the integrated semiconductor memory device, the less sensitive input amplifier is used for generating an internal clock signal. If, by contrast, a lower-noise clock signal is applied to the integrated semiconductor memory device, the control circuit drives the controllable switch in such a way that the more sensitive input amplifier is used for generating the internal clock signal. The changeover of the controllable switch is effected after evaluation of a bit sequence applied to a further input terminal of the integrated semiconductor memory device.

摘要翻译： 集成半导体存储器件包括与第二输入放大器相比相对于其相应输入信号的电平波动具有较低灵敏度的第一输入放大器。 控制电路驱动可控开关，使得当噪声时钟信号被施加到集成半导体存储器件时，较不灵敏的输入放大器用于产生内部时钟信号。 相比之下，如果将低噪声时钟信号施加到集成半导体存储器件，则控制电路以更灵敏的输入放大器用于产生内部时钟信号的方式驱动可控开关。 可控开关的切换在评估施加到集成半导体存储器件的另一个输入端子的位序列之后进行。

公开(公告)号：US06788606B2

公开(公告)日：2004-09-07

申请号：US10284806

申请日：2002-10-31

申请人： Heiko Fibranz ,  Helmut Fischer

发明人： Heiko Fibranz ,  Helmut Fischer

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： In a memory element with a first number of memory cells having a first retention time for holding a content of the memory cells and a second number of memory cells having a second retention time for holding the content of the memory cell, a method for refreshing the memory cells comprises a step of refreshing the first number of memory cells when reaching the first retention time and a step of refreshing the second number of memory cells when reaching the second retention time. An apparatus for refreshing the memory cells of the memory element is provided for refreshing the first number of memory cells when reaching the first retention time, and for refreshing the second number of memory cells when reaching the second retention time.

摘要翻译： 在具有第一数量的存储单元的存储元件中，具有用于保持存储单元的内容的第一保留时间和具有用于保持存储单元的内容的第二保留时间的第二数量的存储单元， 存储单元包括当达到第一保留时间时刷新第一数量的存储器单元的步骤以及在达到第二保留时间时刷新第二数量的存储器单元的步骤。 提供用于刷新存储元件的存储单元的装置，用于在达到第一保留时间时刷新第一数量的存储单元，并且用于在达到第二保留时间时刷新第二数量的存储单元。

公开(公告)号：US06693846B2

公开(公告)日：2004-02-17

申请号：US10446995

申请日：2003-05-27

申请人： Heiko Fibranz

发明人： Heiko Fibranz

IPC分类号： G11C818

CPC分类号： G11C29/12015 ,  G11C11/401 ,  G11C29/50

摘要： A circuit configuration contains a flow controller that can be put into a plurality of states and outputs a respective command, in a respective one of the states, to a circuit component to be controlled. The flow controller has at least one asynchronously operating delay circuit via which the flow controller moves from one of the states into the respective next state. The delay circuit has a further signal path connected in parallel with it which contains a clock-controlled multivibrator. The delay circuit and the further signal path are able to be operated alternatively using a switching device. The circuit allows, particularly in integrated memories, an asynchronous access command sequence, in a first mode, and a synchronous access command sequence, in a second mode, to be produced for the flow controller, particularly in communication with a test unit.

摘要翻译： 电路配置包括可以被置于多个状态的流量控制器，并且将各个状态中的相应命令输出到要被控制的电路部件。 流量控制器具有至少一个异步操作延迟电路，流量控制器通过该延迟电路从一个状态移动到相应的下一个状态。 延迟电路具有与其并联连接的另外的信号路径，其包含时钟控制的多谐振荡器。 延迟电路和另外的信号路径能够使用开关装置交替地操作。 该电路特别是在集成存储器中允许在第一模式中的异步访问命令序列和在第二模式中的同步访问命令序列，用于流控制器，特别是与测试单元的通信。

公开(公告)号：US06366510B2

公开(公告)日：2002-04-02

申请号：US09748473

申请日：2000-12-26

申请人： Heiko Fibranz

发明人： Heiko Fibranz

IPC分类号： G11C700

CPC分类号： G11C29/46

摘要： An electronic memory device (1) having electrically programmable memory cells, an address bus (30) for addressing the memory cells, and also a controllable programming voltage pump (22) for producing a programming voltage for the memory cells. The electronic memory device is distinguished by a switching device (23) which can be actuated by a test mode signal and which can be used to connect the address bus (30) to the programming voltage pump (22) in a test mode such that a prescribable test programming voltage can be set using supplied address bits.

摘要翻译： 一种具有电可编程存储器单元的电子存储器件（1），用于寻址存储器单元的地址总线（30），以及用于产生用于存储器单元的编程电压的可控编程电压泵（22）。 电子存储装置的特征在于可以由测试模式信号致动的开关装置（23），并且可以用于在测试模式下将地址总线（30）连接到编程电压泵（22），使得 可以使用提供的地址位来设置规定的测试编程电压。